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combinational logic
Synthesis Techniques for Masterslice Combinational Logic: A Computer-Aided Evaluation
      
Switch-Level Test-Vector Generation for CMOS Combinational Logic
      
The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic.
      
An improved GA for combinational logic expressions
      
Using combinational logic function to watermark IP based on FPGA
      
The control loop is implemented as a combinational logic circuit on an field-programmable gate array.
      
This paper investigates the effect of injection percentage on the performance of a case-injected genetic algorithm for combinational logic design.
      
In this paper, we propose a case-based reasoning scheme in which we extract domain knowledge (in the form of design patterns) from a genetic algorithm used to optimize combinational logic circuits at the gate level.
      
We model a circuit as a graph in which the vertex setV is a collection of combinational logic elements and the edge setE is the set of interconnections, each of which may pass through zero or more registers.
      
The permutation problem has several applications in the synthesis and verification of combinational logic: it arises in the technology mapping stage of logic synthesis and in logic verification.
      
Evaluation upon problems in combinational logic design does not show any significant performance advantage over other approaches, though does demonstrate a number of interesting behaviors including the preclusion of bloat.
      
The circuit is partitioned into three parts, the input and output combinational logic and the memory.
      
Bounds on the sizes of irredundant test sets and sequences for combinational logic networks
      
We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks.
      
Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits.
      
We describe self-timed circuits, including combinational logic and sequential machines, which either halt or generate illegal output if they include any single stuck-at faults.
      
In this paper, we consider the evaluation of the safety of a self-checking circuit with combinational logic.
      
In this paper we examine a range of gate delay models with respect to their impact on identifying both sensitizable paths and maximum circuit delays in combinational logic circuits.
      
A method for automatic design error location and correction in combinational logic circuits
      
We present a new diagnostic algorithm, based on backward-propagation, for localising design errors in combinational logic circuits.
      
 

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