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Experimental results show that the proposed approach can reduce the computational cost of full search and fast multi-block motion estimation by 80 % and 45 %, respectively, with similar visual quality and bit rate.
      
The proposed algorithm also reduces by 75 % the computational cost of the large-small mode isolation algorithm for low-motion sequence coding, and with 0.06 PSNR gain and 3.7 % reduction in bit rate.
      
In underwater acoustic communication, because the available bandwidth of the channel is severely limited, the direct-sequence spread-spectrum scheme can only be realized at low bit rates.
      
The bit error performance is correlative not only with the interference-signal ratio (ISR), the frequency offset and the phase of the CW interference sensitively, but also with the individual spread spectrum code sequence.
      
DCT_M model for excitation parameter in low bit rate vocoder
      
The description precision of an excitation signal greatly influences the quality of reconstructed speech in low bit rate vocoders.
      
The difference between these two branches of quantum communication is that DSQC requires the two parties exchange at least one bit of classical information for reading out the message in each qubit, and QSDC does not.
      
The throughput of LANs with the DCF mechanism under high load and in noise is evaluated by an analytical method, which ensures high estimation accuracy for any values of protocol parameters and bit error rates.
      
Designs are usually given as Register-Transfer-Level (RTL) specifications, but most of today's hardware verification tools are based on bit-level methods.
      
This information is lost on bit-level and thus cannot be utilized by verification tools, if verification procedures operate on the basis of bit-level descriptions.
      
A method to design tests for the bit-stuck and arbitrary failures of the elements of combinational circuits was proposed.
      
Bit-stuck multiple failures of a limited number of component are permitted, whereas no new failures occur in the course of self-diagnosis.
      
The lowest diversity index was also observed at this pH (1.0-1.5 bit/ind.).
      
The facility is controlled by a computer and contains a programmable galvanizer and 8-bit parallel ADC with a buffer RAM.
      
A 4-channel controller in the 16-bit ISA bus standard on the basis of programmable logic devices is described.
      
It comprises a 4-channel counter, a 4-bit majority coincidence circuit for trigger decision, and a 31-bit timer.
      
The module has 8 analog inputs, 4 analog outputs, and an 8-bit bidirectional port.
      
A CAMAC module is described, which contains four independent 8-bit fast analog-to-digital converters.
      
A 24-bit data acquisition system is developed for recording and processing seismic signals.
      
The recording modules are built on 12-bit ADC with sampling frequencies of 0.5 and 40 MHz and connected by serial fiber-optic communication lines to an interface board, which connects them to an ISA bus.
      
 

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