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circuits
Packings of the complete directed graph with m-circuits
      
A packing of the complete directed symmetric graph DKv with m-circuits, denoted by (v,m)-DCP, is defined to be a family of arc-disjoint m-circuits of DKv such that any one arc of DKv occurs in at most one m-circuit.
      
The packing number P(v,m) is the maximum number of m-circuits in such a packing.
      
The device has been fabricated using standard integrated circuits processing methods combined with the Micro-Electro-Mechanical Systems process.
      
In view of reasonable explanation of intermittent subharmonics and chaos that can be gained from coupling filter between circuits, this paper discusses a method that maps time bifurcation with parameter bifurcation.
      
These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.
      
Practical circuits are fabricated, and the measured results agree well with the simulated results.
      
The study of hybrid model identification, computation analysis and fault location for nonlinear dynamic circuits and systems
      
This paper presents the hybrid model identification for a class of nonlinear circuits and systems via a combination of the block-pulse function transform with the Volterra series.
      
Results show that the method has high accuracy and efficiency for fault location of nonlinear dynamic circuits and systems.
      
Current noise exists in circuits and electronic devices generally, and it exhibits specific features as the system reaches nanometer size.
      
Methods of Decreasing the Complexity of Logic Circuits
      
Realization of combinational circuits on the basis of the expansion of output functions in the class of polynomials is suggested.
      
Logical Modulo Test Circuits: Their Design in Unitary Positional Binary Codes
      
Design of logical circuits for modulo tests in unitary parallel binary code is described.
      
The complexity and speed of circuits designed by different methods are evaluated.
      
Self-Dual Self-Testing Multicycle Circuits: Their Properties
      
Functional testing of memory circuits based on the properties of self-dual functions and a procedure for transforming the initial circuit into a self-dual circuit are described.
      
Experimental results for MCNC benchmark circuits are given.
      
A question is considered as to the development of a procedure of testing combinational circuits with due regard for the power consumed during tests.
      
 

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