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    The Design and Study of Level Two Cache Controller on High Performance DSP Chip
    高性能DSP片内二级Cache控制器设计研究
    In our self-determined design of YHFT_D1, the Second Level Cache Controller (L2), which is programmable, has been adopted.
    在我们自主研制的YHFT_D1中采用片内两级Cache层次,且二级Cache控制器(简称L2)是可编程控制的。
    In order to reduce the miss delay of L2 cache of YHFT-Dx, we further optimized the interface protocol besides adding a direct path from L2 to EMIF. We also set write buffer and adopted 'Requested Word First' technique between data cache and L2, between EMIF and L2, all of which improve the performance of cache system.
    为了减小YHFT-Dx二级Cache的失效延迟,在已增设的1,2与外部存储器接口(EMIF)直接通路基础上进一步优化了接口协议,并通过在EMIF与L2之间、一级数据Cache与L2之间设置写回缓冲和优先供给请求字,大大提高了Cache系统的性能。
    The author is responsible for the design and verification of MMU, L1 cache and L2 cache of "Longtium R2" microprocessor, and then performs in-depth research on the cache hierarchy and consistency of the CMP (Chip Multiprocessor).
    在课题研究中,本文作者主要负责高性能嵌入式微处理器“龙腾R2”的存储管理部件(Memory Management Unit,MMU)、一级Cache和二级Cache的设计和验证。
    2. Based on the successful implementation of "Longtium R2", this paper researched the CMP architecture, analyzed the cache hierarchy and interconnection of the dual core processor and proposed the cooperative cache, which is suitable for "Longtium D2" microprocessor.
    2.在完成“龙腾R2”的研究基础上,对单片多处理器体系结构进行研究,分析了双核处理器Cache层次以及互联结构,并提出适用于“龙腾D2”双核处理器体系结构的协同式二级Cache的设计方案。
    4. Completed the design of the "Longtium D2" L2 cache, including the architecture design, hardware support, interconnection mechanism and the state machine of main controller etc.
    4.完成了“龙腾D2”双核处理器中二级Cache的设计,包括整体结构的设计、硬件支持、互联机制、主控状态机的设计等。
    The cache design support the global and "shared" management of the cooperative cache and support communication between L2 cache.
    支持协同式Cache全局的、“共享”的管理方式以及二级Cache之间的数据传递。
    Generally the processor has on-chip cache,which is composed of fixed-size top level cache(L1Cache)and second level cache(L2Cache). This paper introduces a dynamically configurable cache structure implemented in the embedded processor design.
    一般的处理器芯片都有片上高速缓存Cache,它一般是由固定大小的一级Cache(L1)和二级Cache(L2)构成,文章介绍了一种在嵌入式处理器设计中实现的动态可重构Cache。
    It introduces the architecture of Intel P4 Microprocessor memory, includes L1 data Cache, L2 Cache, Trace Cache;
    文中介绍了P4处理器内存的体系结构,它包括一级数据Cache、二级Cache、TraceCache;
    GridDaen uses two-level cache, which adopts two cache-data tables to locate cache-data and control data access, designs replacing data algorithm in its cache, and provides a set of flexible config methods which can separate cache from client or server and implement scalable cache in client or server.
    GridDaen采用二级Cache机制,使用两个数据缓冲表来快速定位缓冲数据和控制缓冲数据访问,给出了各级Cache的数据替换算法,并提供了灵活的配置方法,可以将Cache与客户机、服务器独立分布,实现了Cache的可扩展性。
    The Leakage Power Optimization in On-Chip L2 Caches
    片内二级Cache的静态功耗优化技术研究
    In this thesis, the following results have been achieved:1. Performance analysis of string matching algorithm: Through experimental and theoretical analysis, the linear correlation between the execution time and level 2 cache misses of algorithm was illustrated. This thesis analyzed the time complexity of the classic algorithm (eg. AC.Wu-Manber, SBOM) and proposed two optimization strategies: compressing the string matching automata's memory space and improving its locality.
    1.串匹配算法性能分析:通过实验和理论分析,本文得出串匹配算法的执行时间和二级cache miss之间的线性关系,并对经典算法的时间复杂度进行了分析,提出了从压缩存储空间和改善数据结构局部性这两方面来优化串匹配算法的途径。
    Proposed the L2 cache design of "Longtium D2" that is a dual core microprocessor.
    在此基础上,对双核系统中Cache的层次结构和一致性问题进行了深入的研究,并提出双核处理器“龙腾D2”二级Cache的设计方案。
    1. Performed systematic research on Memory Management and cache control of the High Performance Microprocessor. Then the Memory Management Unit, L1 Cache and L2 cache which are compatible with PowerPC instruction set are designed and implemented. The simulation results and analysis prove that it is fully compatible with PowerPC750 in function.
    1.对高性能微处理器中的存储管理和Cache组织控制方法进行了系统研究,在研究的基础上,设计并实现了适应PowerPC指令集系统结构的存储管理单元、一级Cache以及二级Cache,并应用于“龙腾R2”微处理器中,经仿真分析,其功能和PowerPC750完全兼容。
    To reduce the access time which can increase the holistic capability of microprocessor, P4 microprocessor adopts these ways: hiberarchy-design, bulky L2 Cache and applying prefetcher which can increase the hit rate of cache and reduce the cost of hit failed.
    P4处理器主要采取具有层次结构的内存设计、大容量的二级Cache和在跟踪Cache中采用预取处理机制的方法来提高Cache的命中率和降低未命中的代价来缩短处理器的访问时间,最终达到提高处理器整体性能的目的。
    (3)Presenting timing-move and replacing according to a given threshold strategy. This strategy is moving the small data blocks which are accessed lately in level 2 caches node to level 1 cache, and replacing the level 2 caches node when small data blocks moved exceeds a given threshold.
    (3)提出了定时搬移并按阈值淘汰的策略 ,即定时把二级 Cache的节点中最近访问过的数据小块搬移到一级 Cache,当搬移的数据小块超过一个阈值时 ,淘汰二级 Cache的相应节点 .
    The cache comprises of a virtual memory pagefile and part of system RAM. It takes full use of the performance differences between different disk access modes.
    这种层次Cache使用虚存页面文件和部分系统RAM组成二级Cache结构,能很好地利用磁盘访问在大/小写以及随机/顺序访问时的巨大性能差异。
    1 gives the diagram of the architecture of the "Longtium" R2.Section 2 discusses in detail L1 Cache. Fig. 2 explains the architecture of L1 instruction cache.
    论文提出了一种设计32位超标量微处理器Cache单元的结构,讨论了一级Cache、二级Cache设计中的关键技术,介绍了Cache一致性协议的实现,满足了“龙腾”R2微处理器芯片的设计要求。
 

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