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    Large-scale Combinational Logic IC of K-type Architecture
    K式结构大规模组合逻辑集成电路
    AN IMPROVEMENT ALGORITHM OF CAD SOFTWARE OF MULTIPLE OUTPUT COMBINATIONAL LOGIC TWO STAGE CIRCUIT
    综合多输出组合逻辑二级电路CAD软件算法的改进
    A TEST FAULT MODEL FOR COMBINATIONAL LOGIC CIRCUITS
    组合逻辑电路的测试故障模型
    APPLICATION OF DUALITY PRINCIPLE IN DESIGNING OF COMBINATIONAL LOGIC CIRCUIT
    对偶原理在组合逻辑电路设计中的应用
    CLES-An Expert System for Combinational Logic Synthesis
    一个组合逻辑综合专家系统的设计与实现
    Dynamic Max—covering Method for Simplifying Combinational Logic Functions
    组合逻辑函数化简的动态极大复盖法
    Backward Analysis and Conditional Path Method for Combinational Logic Circuits
    组合逻辑电路的逆向分析和条件通路法
    A NEW METHOD OF SEQUENTIAL LOGIC SYNIHESIS BASED ON COMBINATIONAL LOGIC MINIMIZATION
    基于组合逻辑最小化技术的时序逻辑综合方法
    On the Design about Un-inversion Variable Input of Combinational Logic Cricuit
    组合逻辑电路的无反变量输入设计
    An Advance Probe Method for Automatic Synthesize of Combinational Logic Circuitsc
    组合逻辑自动综合的超前试探法
    Application of stuctured approach in combinational logic circuits design
    结构优化设计方法在组合网络设计中的应用
    An Algorithm for Generating the Least Complete Detection Set of Combinational Logic Circuit
    一种求解组合逻辑电路最小完全检测集的算法
    Application of First Degree Boolean Difference for Test Generation of Combinational Logic Circuit
    一阶布尔差分在组合逻辑电路测试生成中的应用
    An Investigation into the Application of OBDD to the Test Generation of Combinational Logic Circuits
    OBDD在组合逻辑电路测试中的应用研究
    A Design for Combinational Logic Circuit Using PLA
    利用PLA设计时序逻辑电路
    Study of a Simplification Method Using the Karnaugh Map for Multi-Output Combinational Logic Functions
    多输出组合逻辑函数共卡诺图化简法的研究
    A New Method for the Design and Realization of the Minimizer for Combinational Logic Circuits
    一种新的基于最小项逻辑优化的软件设计与实现
    A Transition Count Testing of Multi - output Combinational Logic Circuits
    多输出电路跳变次数(TC)测试算法
    Minterm-Encoding Based Algorithms :the Design and Realization of the Mimizer for Combinational Logic Circuits
    基于编码算法的组合逻辑电路最优化软件的设计与实现
    The method of judge and remove in the phenomenon of race and hazard of the combinational logic circuit
    组合逻辑电路中的竞争冒险现象的判断和消除
 

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