The “three-path” latch-up window model is simply based on the analysis of CMOS device latch-up circuit model.
A OSCILLATING BLOCK CIRCUIT BASED ON d|Ucosφ|/dt PRINCIPLE
A CMOS Undervoltage Lockout of Hysteretic Threshold of Zero Temperature Coefficients
The circuit can be used to prevent latchup in conventional bulk-Si CMOS devices.
A low cost, simple architecture, zero temperature coefficient undervoltage lockout circuit with hysteresis base on standard CMOS process is proposed in the paper.
本文采用CMOS工艺设计了一种带迟滞的零温度系数的欠压 闭锁电路。 与传统的采用BiCMOS工艺设计的电路相比, 本文电路工艺成本低,易于实现。
The zero temperature coefficient threshold voltage is generated by bandgap structure, which significantly enhances the accuracy of the under voltage lockout threshold and temperature property; additionally, the hysteresis is realized by using a feedback circuit to overcome the bad disturbance and noise rejection of the single threshold.
CMOS circuits latch up induced from ionization and latch up elimination methods
电离引起的CMOS 电路 闭锁及消除方法
Basic Direct Current Circuits
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In conclusion, NDR devices based upon a conjugated polymer platform were developed and applied towards a latching circuit.
These positive transitions are fed into the CA3059, which is used as a latching circuit and zero crossing triac driver.
The fabricated RITD-HBT can readily function as a latching circuit element.
A more detailed hypothesis for a latch circuit is developed below in A model of the latch circuit.
By making the latch circuit independent of motor error, the effect of time jitter on movement accuracy is significantly reduced.
Robinson's original gate circuit acts as a latch circuit because it feeds back the output of the pulse generator to the suppressor cell.
The delay required to track the dropped pulses was obtained using a cascade of RF switches, controlled by a latch circuit.
The latch circuit means a circuit operated an external signal over Latch threshold voltage of MultFP terminal.