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时序线路
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  sequential circuit
     Multiple Fault Testing of Synchronous Sequential Circuit with Dynamic Boolean Equation Method
     同步时序线路多故障测试的动态布尔方程方法
短句来源
     The multiple fault testing of synchronous sequential circuit with the dynamic Boolean equation method which reduces the Exclusive-OR operation to the logic addition one is proposed.
     本文提出了同步时序线路多故障测试动态布尔方程方法,它将同步时序线路中的“异或”运算归结为逻辑加运算,可一次求出被测线上双固定型故障s-a-1和s-a-0的全部测试集.
短句来源
     So far, there are no perfect methods for designing sequential circuit, while researches on designing stochastic circuit are even fewer.
     时序线路的设计方法迄今仍不很完善,而随机型逻辑线路的设计就研究得更少。
短句来源
     At the beginning of the paper, we outline the main results of Star Algorithm, and then by examples describe the procedure by which the tests of a sequential circuit can be generated. Afterwards we compare it with D Algorithm and Nine-Valued Algorithm.
     文章开始,首先扼要介绍星算法的主要结果,然后通过例子详细描述利用星算法产生时序线路测试的过程,并与D算法和9值算法进行了比较。
短句来源
     In this article,CP in asynchronous sequential circuit is discus se d.
     论述了异步时序线路特征表达式中的CP脉冲.
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  “时序线路”译为未确定词的双语例句
     The principle and method for designing the multivariable—multistate sequential circuits by the state flip-flop matrix and coded matrix are introduced.
     文中介绍了用状态触发矩阵、编码矩阵设计多变量多状态时序线路和离散系统的原理与方法,着重讨论了时序线路的数学模型、建立状态触发矩阵和编码矩阵、应用有关定理及公式作技术实现等问题。
短句来源
     A Near Optimal Algorithm for Test Generation in Sequential Circuits-Star Algorithm
     时序线路测试生成的一个较优算法——星算法
短句来源
     STATISTICAL TESTING FOR SEQUENTIAL CIRCUITS
     时序线路的统计测试
短句来源
     The Discussion on CP in Asynchronous Sequentical Circuit
     论异步时序线路特征表达式中的CP
短句来源
     Introduced is the canonical form of μ-Petri nets with which μ-Petri nets are transformed into typical asynchronous sequential circuits. Then the transition/output table (i.e. coded flow table) is written out on condition of allowed set of input sequences.
     引入μ-Petri网的标准型式后,将μ-Petri网转换成标准的异步时序线路,再写出此异步时序线路在容许输入序列集下的转移/输出表(编了码的流程表)。
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  相似匹配句对
     STATISTICAL TESTING FOR SEQUENTIAL CIRCUITS
     时序线路的统计测试
短句来源
     transportation line and time sequence planning of part.
     零部件运输线路时序规划。
短句来源
     Timing Verification of X Microprocessor
     X微处理器时序验证
短句来源
     Time-series Rules Mining
     时序规则挖掘
短句来源
     The Debate of Cultural Routes
     文化线路辨析
短句来源
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  sequential circuit
These are real-world problems concerning a sequential circuit that is part of a commercial chip manufactured by Texas Instruments.
      
Sequential circuit realizations with pulse input fundamental mode sequential circuits
      
This paper gives a unified treatment for electronic sequential circuit realizations and suitable procedures for synthesizing them.
      
This is done by showing that every sequential circuit operating in synchronous mode can be transformed into an equivalent sequential circuit operating in fundamental mode with the same number of internal states.
      
The implemented algorithm translates a system description written in a transfer language into a set of flow-tables, each one representing a sequential circuit of the system.
      
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In this paper is investigated design methodology in accordance with which implementation of μ-Petri nets by multimicroprocessor may be procceded. μ-Petri nets are defined, and they are used to describe the struetures of a significantly wide class of parallel asynchronous processes. Introduced is the canonical form of μ-Petri nets with which μ-Petri nets are transformed into typical asynchronous sequential circuits. Then the transition/output table (i.e. coded flow table) is written out on condition of allowed...

In this paper is investigated design methodology in accordance with which implementation of μ-Petri nets by multimicroprocessor may be procceded. μ-Petri nets are defined, and they are used to describe the struetures of a significantly wide class of parallel asynchronous processes. Introduced is the canonical form of μ-Petri nets with which μ-Petri nets are transformed into typical asynchronous sequential circuits. Then the transition/output table (i.e. coded flow table) is written out on condition of allowed set of input sequences. If the given μ-Petri net and, in particular, the number of its places are considersbly large, the corresponding multimictoprocessor architecture is presented, decomposing the transition/output table. An example based on the microcomputer family M6800 is used to illustrate the implementation of μ-Petri nets by multimicroprocessor system.

本文探讨在以多微处理机实现μ-Petri网(一种加以半解释的安全Petri网)这一工作中可遵循的设计方法论。先定义μ-Petri网可描述相当广泛类型的并行异步过程的控制结构。引入μ-Petri网的标准型式后,将μ-Petri网转换成标准的异步时序线路,再写出此异步时序线路在容许输入序列集下的转移/输出表(编了码的流程表)。分裂转移/输出表(如果给定的μ-Petri网规模相当大,特别是p结点为数相当多,因而此表也相应大),提出相应的多微处理机总体结构。以M—6800微计算机族为例,阐明如何实现μ-Petri网成多微处理机系统。

In this paper we discuss how to apply star Algorithm(1) to test generation for sequential circuits. The circuit under test may be asynchronous. The basic logic unit may be gate-level or function-level unit. Besides, the algorithm is capable of self-initialization. At the beginning of the paper, we outline the main results of Star Algorithm, and then by examples describe the procedure by which the tests of a sequential circuit can be generated. Afterwards we compare it with D Algorithm and Nine-Valued Algorithm....

In this paper we discuss how to apply star Algorithm(1) to test generation for sequential circuits. The circuit under test may be asynchronous. The basic logic unit may be gate-level or function-level unit. Besides, the algorithm is capable of self-initialization. At the beginning of the paper, we outline the main results of Star Algorithm, and then by examples describe the procedure by which the tests of a sequential circuit can be generated. Afterwards we compare it with D Algorithm and Nine-Valued Algorithm. In fact, Star Algorithm seems to have more advantages than the others.

本文讨论星算法在时序线路测试生成中的应用。被测时序线路可以是异步的,基本逻辑单元可以是门级或功能级元件,此外,算法具有自初始化的能力。文章开始,首先扼要介绍星算法的主要结果,然后通过例子详细描述利用星算法产生时序线路测试的过程,并与D算法和9值算法进行了比较。事实表明,星算法较之其它算法,具有更多的优点。

In this paper a new logical design methodology is investigated. Being capable of passing by the flow table with its subsequent reduction and coding as the classical method required, one implements directly the explicit equations of predicate calculus t formulas on synchronous sequential circuits. In the implementation, memory elements are not restricted to delay elements or D flip-flops and various standard flip-flops can also be used. Presented first is a general implementation method and then some specificimplementation...

In this paper a new logical design methodology is investigated. Being capable of passing by the flow table with its subsequent reduction and coding as the classical method required, one implements directly the explicit equations of predicate calculus t formulas on synchronous sequential circuits. In the implementation, memory elements are not restricted to delay elements or D flip-flops and various standard flip-flops can also be used. Presented first is a general implementation method and then some specificimplementation techniques are studied.

本文探讨了直接实现(不经过流程表及其简化、编码等手续)谓词演算t式显式方程组成同步时序线路的逻辑设计方法。实现中容许使用各种触发器作记忆元件,而不仅只限于延迟元件或D触发器。先论述一般实现方法,后探讨各种特殊的实现技术。

 
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