助手标题  
全文文献 工具书 数字 学术定义 翻译助手 学术趋势 更多
查询帮助
意见反馈
   低功耗测试 的翻译结果: 查询用时:0.739秒
图标索引 在分类学科中查询
所有学科
无线电电子学
更多类别查询

图标索引 历史查询
 

低功耗测试
相关语句
  low power testing
     Several Methods of Low Power Testing in System on a chip
     系统芯片中低功耗测试的几种方法
短句来源
     Research on VLSI Low Power Testing Technology
     集成电路低功耗测试方法研究
短句来源
     This paper introduces some basic concepts and modeling methods in low power testing, analyzes the causes of increased power consumption, discusses some current practices of power optimization, and finally presents an at speed low power self testing method for the high performance microprocessor.
     首先介绍低功耗测试技术中的基本概念和功耗建模方法 ,分析测试过程中功耗升高的原因 ,对已有的几种主要的降低测试功耗方法进行详细分析 ,最后给出一种高性能微处理器的真速低功耗自测试方法
短句来源
     Low power testing scheme has been paid more attention because of low power design.
     随着低功耗设计的兴起,低功耗测试正在得到越来越多的关注。
  low power test
     Theory of Modeling and Analyzing on Low Power Test Sequences Generation Circuit
     低功耗测试序列生成电路的建模及分析
短句来源
     A Low Power Test Generator Design Using FPGA
     基于FPGA的低功耗测试生成器的设计
短句来源
     2 In mixed-mode BIST low power test scheme, the gating of system clock scheme is applied to achieve pseudo-random low power test, and utilize the characteristic of the folding sequences at the phase of deterministic test to gain low power dissipation test.
     2 提出了一种混合BIST低功耗测试方案:根据混合BIST测试方案的特点,利用门控时钟测试方法实现了混合BIST中伪随机低功耗测试;
短句来源
     The principle of the proposed technique is firstly to utilize automatic test pattern generator tools to generate deterministic test patterns with short length and high fault coverage, then the generated patterns are sorted to get low power test sequence, and finally the BIST circuit description is automatically generated by selecting finite state machine optimization and synthesis scheme.
     先对原型设计用自动测试图形工具生成长度短、故障覆盖率高的确定性测试图形,然后对生成的图形排序以取得低功耗测试序列,再选择状态机优化和综合方案,最后自动生成BIST电路描述.
短句来源
  “低功耗测试”译为未确定词的双语例句
     Aiming at Low-Power BIST, a novel low-power BIST scheme was presented.
     针对低功耗测试问题,本文提出一种新的低功耗混合BIST方案。
短句来源
     3 The scheme of complete deterministic low power BIST test is brought forward. Firstly, the minimum set of seeds that LFSR and folding counter encoded the complete deterministic test vectors is acquired. The seeds can stored at ROM in CUT or test equipments.
     3 完全确定性BIST低功耗测试方案研究:针对电路完全确定性测试集的特征,结合LFSR和折叠压缩双重编码方案,完成对完全确定性测试集的编码,并将编码之后获得的折叠种子存储在被测电路ROM中或者是自动测试设备存储单元中。
短句来源
     For low power consumption during test mode, the proposed approach ignores the non detecting vectors by altering the structure of LFSR.
     通过改变线性反馈移位寄存器的结构滤掉无效的测试矢量从而实现低功耗测试
短句来源
     RSIC (random single-input change) sequence generation is an advance research topic to very deep submi-cron IC, core-based IC and low power IC testing.
     为了解决深亚微米、SOC和低功耗电路中的测试问题,低功耗测试序列RSIC序列的生成方法得以研究和发展。
短句来源
查询“低功耗测试”译词为用户自定义的双语例句

    我想查看译文中含有:的双语例句
例句
为了更好的帮助您理解掌握查询词或其译词在地道英语中的实际用法,我们为您准备了出自英文原文的大量英语例句,供您参考。
  low power testing
A Gated Clock Scheme for Low Power Testing of Logic Cores
      
On completing this course, trainees should understand the essential testing techniques and be capable of applying low power testing techniques.
      
The proliferation of portable devices has motivated research in the domain of low power testing.
      
  low power test
Low power test application has become important in today's VLSI design and test.
      
Section II describes the proposed technique for low power test pattern generation.
      
The output angle was checked from the intensity and phase measurements in the low power test.
      
  low-power test
A low-power test at a frequency of 106.4 GHz has been carried out for several polarizers with different groove depths.
      
The MLS approach is capable of providing vastly superior dynamic range in comparison to the straightforward technique using an impulse excitation and is thus an optimal solution for measurements in noisy environments and for low-power test signals.
      
A low-power test-per-scan BIST architecture with a scan chain of m latches B.
      
An experimental low-power test cell has been integrated, showing 100pV equivalent offset voltage, and input noise equal to 270 KV.
      
Rocket-triggered testing should also be performed on a facility similar to one of the Pantex NEAs to confirm the low-power test results.
      
更多          


Considering power optimization in design for testability of system-on-a-chip is a newly emerging research region. Its main reason is that the power assumption of digital circuits in test mode is very higher than that in normal system operation mode. Power during testing can make system cost high, reliability low,yield down. In this paper, some basic concepts of low power testing techniques are introduced. Some main existing methods of reducing testing power are analyzed. At the last,the development trends and...

Considering power optimization in design for testability of system-on-a-chip is a newly emerging research region. Its main reason is that the power assumption of digital circuits in test mode is very higher than that in normal system operation mode. Power during testing can make system cost high, reliability low,yield down. In this paper, some basic concepts of low power testing techniques are introduced. Some main existing methods of reducing testing power are analyzed. At the last,the development trends and some problems needed to resolve are pointed out.

在系统芯片可测试性设计中考虑功耗优化问题是当前国际上新出现的研究领域。在可测试性设计中考虑功耗的主要原因是数字电路在测试方式下的功耗比系统在正常工作方式下高很多。测试期间的功耗会引发系统成本上升,可靠性降低,成品率下降。本文介绍低功耗测试技术中的一些基本概念,对已有的几种主要的降低测试功耗方法进行分析,最后给出一种高性能微处理器的真速低功耗自测试方法。

In this paper a new low power BIST methodology by altering the structure of linear feedback shift register (LFSR) is proposed. In pseudo random test mode, the efficiency of the vectors decreases sharply as the test progresses. For low power consumption during test mode, the proposed approach ignores the non detecting vectors by altering the structure of LFSR. Note that altering the sturcture of LFSR is efficient, and it has no impact on the fault coverage.

本文提出了一种通过改变线性反馈移位寄存器 (LFSR)的结构实现低功耗内建自测试方法。在伪随机测试方式下 ,随着测试的进行 ,测试矢量的效率大幅降低。通过改变线性反馈移位寄存器的结构滤掉无效的测试矢量从而实现低功耗测试。实践证明 ,改变线性反馈称位寄存器的结构的方法是有效的并且对故障覆盖率没有影响

Reducing the power consumption in design for testability is a new research field in the academic and industrial circles. The main reason is that the power consumption of digital circuits in test mode is much higher than that in normal system operation mode. Power consumption in testing causes the system's high cost, low reliability and productivity. This paper introduces some basic concepts and modeling methods in low power testing, analyzes the causes of increased power consumption, discusses some current practices...

Reducing the power consumption in design for testability is a new research field in the academic and industrial circles. The main reason is that the power consumption of digital circuits in test mode is much higher than that in normal system operation mode. Power consumption in testing causes the system's high cost, low reliability and productivity. This paper introduces some basic concepts and modeling methods in low power testing, analyzes the causes of increased power consumption, discusses some current practices of power optimization, and finally presents an at speed low power self testing method for the high performance microprocessor.

降低测试期间的功耗是当前学术界和工业界新出现的一个研究领域。在可测试性设计中进行功耗优化的主要原因是数字系统在测试方式的功耗比在系统正常工作方式高很多。测试期间功耗会引发成本增加 ,可靠性降低 ,成品率下降。首先介绍低功耗测试技术中的基本概念和功耗建模方法 ,分析测试过程中功耗升高的原因 ,对已有的几种主要的降低测试功耗方法进行详细分析 ,最后给出一种高性能微处理器的真速低功耗自测试方法

 
<< 更多相关文摘    
图标索引 相关查询

 


 
CNKI小工具
在英文学术搜索中查有关低功耗测试的内容
在知识搜索中查有关低功耗测试的内容
在数字搜索中查有关低功耗测试的内容
在概念知识元中查有关低功耗测试的内容
在学术趋势中查有关低功耗测试的内容
 
 

CNKI主页设CNKI翻译助手为主页 | 收藏CNKI翻译助手 | 广告服务 | 英文学术搜索
版权图标  2008 CNKI-中国知网
京ICP证040431号 互联网出版许可证 新出网证(京)字008号
北京市公安局海淀分局 备案号:110 1081725
版权图标 2008中国知网(cnki) 中国学术期刊(光盘版)电子杂志社