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cmos工艺     
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  cmos technology
    DC and AC Characteristics of Lateral Bipolar Transistors Compatible with CMOS Technology
    CMOS工艺中横向双极型晶体管的直流与交流电学特性
短句来源
    Fabrication of LateraliMagnetotransistor Using Buried p-Layer CMOS Technology
    用p埋层CMOS工艺制造横向磁敏晶体管
短句来源
    A New Algorithm for DC Charicteristics of Lateral Bipolar Transistors Compatible with CMOS Technology
    与CMOS工艺兼容的横向双极晶体管直流特性的新算法
短句来源
    Implemented in TSMC's 0.18 μm 6-metal mixed-signal/RF CMOS technology,the circuit consumes 30 mA of current from a 1.8 V power supply.
    电路采用TSMC 0.18μm 6层金属混合信号/射频CMOS工艺实现。 在1.8 V电源电压下,静态电流为30 mA。
短句来源
    A monolithic LC-tuned voltage controlled oscillator(LC-VCO)with low phase noise is fabricated with TSMC 0.18μm RF(radio frequency)CMOS technology.
    采用TSMC0.18μm射频CMOS工艺设计了一个具有低相位噪声的单片LC调谐型压控振荡器.
短句来源
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  cmos process
    A Study on 2μm CMOS Process Engineering
    2微米CMOS工艺工程技术研究
短句来源
    The Application of All Ion-Implantation to Si-gate CMOS Process
    全离子注入技术在硅栅CMOS工艺中的应用
短句来源
    A Linear Magnetic Field Sensor Fabricated by CMOS Process with p Buried Layer
    采用p型埋层CMOS工艺制备线性磁场传感器
短句来源
    A2-μm p-Well CMOS process
    一种2μmp阱CMOS工艺
短句来源
    Improving Source-Drain Punch-Through Voltage in 2-μm p-Well CMOS Process
    2μmp阱CMOS工艺中提高源-漏穿通电压的方法
短句来源
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  cmos technics
    A Limiting Amplifier Design of Basing on CMOS Technics
    基于0.6μm CMOS工艺的限幅放大器设计
短句来源
    In this paper, two CORDIC modules have been designed and ASIC synthesis and FPGA verifies is completed . The result indicates that the work frequency can reach 190MHz under 0.35 μm CMOS technics.
    本文设计了两个CORDIC模块,在0.35/μm的CMOS工艺下完成了ASIC综合,其最高工作频率可以达到190MHz。
短句来源
    Two 32 bits RISC CPU are designed, which have been verified with FPGA, the ASIC synthesis of CPU1 has been completed and its work frequency can reach 230MHz under 0.35 μm CMOS technics.
    设计了两个32位RISC CPU模块,它们都完成了FPGA验证,其中CPU1还完成了ASIC前端设计,在0.35/μm的CMOS工艺下,最高工作频率可达到230MHz。
短句来源
    To avoid the high temperature process in Si/SiGe CMOS technics,appropriate implantation energy and dose and RTP(rapid thermal anneal) are introduced into the the fabrication of Si/SiGe CMOS double-well and source.
    为避免应变Si沟道(Strained Si channel)CMOS工艺中的高温过程,通过选择合适的离子注入能量和剂量,采用快速热退火(RTP)工艺,制备出适合做应变Si沟道CMOS的双阱及源漏。
短句来源
    SOI CMOS technology is used in some special application field,and it has many ascendancy. We are succeed in making good IC what has high anti-radiation capability of using SIMOX and 0.8μm SOI CMOS technics. In last we give a change relation of SOl CMOS IC's identity with relation dosage.
    SOI CMOS技术在一些特殊应用领域中有着体硅无法比拟的优势文中叙述采用SIMOX材料和0.8μm SOI CMOS工艺加固技术成功研制出抗辐射性能较好的器件和电路,并且给出了SOI CMOS器件的特性随辐照总剂量的变化关系,试验电路通过了总剂量500 Krad(Si)钴60γ射线辐照实验。
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  “cmos工艺”译为未确定词的双语例句
    Fully Phosphorus-Doped PolysiIicon Gate Technology for 5μm CMOS ICs
    5微米全掺磷封闭硅栅CMOS工艺
短句来源
    FULLY PHOSPHORUS-DOPED POLYSILICON GATE TECHNOLOGY FOR 5μm CMOS ICS
    5微米全掺磷硅栅CMOS工艺
短句来源
    Submicron CMOS Titanium Silicide Technology
    亚微米自对准硅化钛CMOS工艺
短句来源
    Based on SMIC 0.18μm CMOS standard cell library, the design is synthesized. The estimated area is 0.38mm2, clock frequency is up to 166MHz.
    本设计在中芯国际0.18μm CMOS工艺标准单元库的基础上进行综合,硬件加速器面积为0.38mm2,工作时钟频率可达166MHz。
短句来源
    Fully differential folded-cascode structure was adopted and fabricated in a 0.35 μm CMOS mixed mode process with a single 3 V supply.
    该电路采用全差分折叠-共源共栅结构,采用0.35μm CMOS工艺实现,工作于3 V电源电压。
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  cmos technology
Photoresists Used as Mask Materials in Ion Implantation for the CMOS Technology: Optimizing Mask Thickness
      
The integrator is intended to operate in ΣΔ-modulation ADCs realized in basic CMOS technology.
      
The structures are fabricated by CMOS technology on the same n-Si wafer, the NMOS structures being formed in a p-well.
      
A fifth-order Chebyshev LPF with a 1-MHz cutoff frequency is thus synthesized and fabricated in a 0.35-μm CMOS technology.
      
The data examined are obtained by measurements on ICs fabricated by a 0.25-or 0.18-μm established CMOS technology.
      
更多          
  cmos process
The chip was fabricated in 0.35 μm 1P3M standard CMOS process.
      
It is analyzed in theory and simulated with Spectre based on 0.25μm CMOS process.
      
Single-Pole Double-Throw (SPDT) broadband switch has been designed in a 0.25μm Complementary Metal Oxide Semiconductor (CMOS) process.
      
The designed circuits are fabricated by 0.6 μm CMOS process.
      
The circuit occupies 0.03 mm2 using a 0.6 μm, 2M/2P, standard CMOS process, and consumes 0.25 mW at 5 V.
      
更多          


Based on the theory of NMOS design rules developed by Mead and Conway and CMOS features, concept of mixed design rules and its applications in Si-gate LOCOS CMOS technology are proposed. The typical geometrical and electrical parameters of the mixed design rules re given in this paper. The typical characteristics of CMOS ring oscillators, D-type flip/flops and operational amplifiers designed according to the mentioned rules are also described. Finally, standard colours and graphic representations for CMOS layout...

Based on the theory of NMOS design rules developed by Mead and Conway and CMOS features, concept of mixed design rules and its applications in Si-gate LOCOS CMOS technology are proposed. The typical geometrical and electrical parameters of the mixed design rules re given in this paper. The typical characteristics of CMOS ring oscillators, D-type flip/flops and operational amplifiers designed according to the mentioned rules are also described. Finally, standard colours and graphic representations for CMOS layout design are recommended.

本文根据Mead和Conway提出的NMOS集成电路设计规则理论及CMOS特点,提出了混合型设计规则概念及其在硅栅等平面CMOS工艺中的应用,给出其几何及电学设计规则的典型值以及根据此规则试制成功的CMOS环形振荡器、D触发器、运算放大器等集成电路的典型特性。最后,本文还建议了设计CMOS电路应采用的标准颜色及符号。

This paper describes a technique of nigh speed CMOS logic circuits with 3-μm silicon gate. The technique which is based on some key process researches such as fine stracture lithography, dry etch, control and modulation of threshold voltage etc, have developed early in the 80s only.The typical parameters of CC74HC circuits are 8ns for maximum propagation delay time, 55MC for maximum operation frequency and 20pf for power dissipation caqacitance.

CMOS工艺将成为VLSI电路的主流.本文所介绍的我们研制成功的3微米硅栅高速CMOS逻辑电路工艺;是在八十年代初国外刚开发成功推出的产品.该工艺开发的CC74HC系列电路.因采用3微米多晶硅栅自对准工艺。大大缩小了芯片尺寸,基本上消除了栅与源、漏的覆盖电容,使器件工作速度提高到8ns/门,触发器最大工作频率为55MC.这种电路的管脚排列与低功耗肖特基TTL(LSTTL)可互换,而功耗远低于LSTTL电路.本文对研制中的关键工艺作了讨论,并将产品与国外同类产品的主要参数作了比较.

This paper describes the physical mechanism of the negative resistance breakdown (NRB) effect in high voltage NMOS integrated devices and the criterions of the effect have been proposed. Based on the theoretical model of NRB effect, a novel dual-gate high voltage NMOS integrated device with NRB-free has been developed using a fabrication process fully compatible with the n-well Si-gate CMOS VLSI technology without any additional process steps. The driaa breakdown voltage greater than 300V over the range of gate...

This paper describes the physical mechanism of the negative resistance breakdown (NRB) effect in high voltage NMOS integrated devices and the criterions of the effect have been proposed. Based on the theoretical model of NRB effect, a novel dual-gate high voltage NMOS integrated device with NRB-free has been developed using a fabrication process fully compatible with the n-well Si-gate CMOS VLSI technology without any additional process steps. The driaa breakdown voltage greater than 300V over the range of gate voltage 0-10V has been achieved. For the unit aspect ratio, the device has shown the saturated drian current greater than 0.3mA and the on-resistance loss than 44kΩat 10V of the gate voltage.

本文讨论了高压NMOS集成器件中负阻击穿观象的机理。给出了发生负阻击穿的判定条件,建立了模型。 采用与目前国际上先进的主流工艺——n阱硅栅等平面CMOS工艺完全兼容的工艺流程,且无需增加任何工艺步骤,研制成一种新型的无负阻击穿的双栅型高压NMCS器件。在栅压为0~10V时,其漏源击穿电压大于300V,最大饱和电流大于0.3mA/单位宽长比(栅压为10V时),导通电阻为44kΩ·单位宽长比(栅压为10V时),具有广泛的应用价值。

 
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