助手标题  
全文文献 工具书 数字 学术定义 翻译助手 学术趋势 更多
查询帮助
意见反馈
   微处理器内核 的翻译结果: 查询用时:0.486秒
图标索引 在分类学科中查询
所有学科
计算机硬件技术
更多类别查询

图标索引 历史查询
 

微处理器内核
相关语句
  microprocessor core
     Low Power Design of an 80C51 Embedded Microprocessor Core
     80C51嵌入式微处理器内核的低功耗设计
短句来源
     Design of an Embedded Microprocessor Core OM80C51 Using the Divide-and-Conquer Strategy
     应用分割取胜策略设计的嵌入式微处理器内核OM80C51
短句来源
     Synthetic VHDL Microprocessor Core Design
     VHDL语言设计可综合的微处理器内核
短句来源
     The low power design of an 80C51 embedded microprocessor core is prese nted in this paper.
     介绍了一种80C51嵌入式微处理器内核的低功耗设计方法。
短句来源
     Advances in Power Supplies for Portable Microprocessor Core Voltages
     便携式微处理器内核电源电压的改进
短句来源
更多       
  “微处理器内核”译为未确定词的双语例句
     OM80C51 is compatible with 80C51. Some of its performances are better than those of 80C51. It provides shorter instruction cycles for most instructions, and some effective technologies are used in power management, and it has a customized interrupt system and periphery circuits.
     OM80C51是一个与80C51兼容但在性能上有一定改进的嵌入式微处理器内核
短句来源
     The mobile geographic information terminal hardware platform researched in this article has based on the 32 bit embed microprocessor (S3C2410) provided by Sam s-ung Co. The kernel of S3C2410 has grounded on ARM920T and it offers plenty o f periphery joints. This article makes the best of abundant resources supplied by S3C -2410 in design.
     本文主要工作是设计开发基于32位嵌入式微处理器(S3C2410)的移动地理信息终端硬件平台,S3C2410微处理器内核架构基于ARM920T。
短句来源
     By using single-chip microcomputer C8051F060 and DDS AD9852, the instrument is easy to measure the transport characteristic of the high frequency tuner. By using C8051F060 to control DDS chip AD9852, a signal with high resolution, high transferring speed and pure spectrum is obtained. The output frequency range is up to 1000MHz.
     采用Cygnal公司的专利CIP51微处理器内核的C8051F060单片机作为控制器,使用锁相环+直接数字合成+下变频的方法构成扫频信号源,用直接数字频率合成(DDS)芯片AD9852实现扫频信号的控制,产生测量用的扫频信号的范围为1~1000MHz。
短句来源
     Linux is an open and free operation system; ARM is an excellent 32-bit RISC CPU core, and most powerful Embedded CPUs are designed on the base of ARM.
     Linux操作系统是个开源、免费的操作系统,ARM是当前全球领先的16/32位RISC微处理器内核,现在大多数功能强大的嵌入式处理器都基于ARM内核构建。
短句来源
     Thread level parallel processing is one of the key technologies for modern processor design, which improves the processor performance and resource utilization effectively.
     线程级并行技术能有效的提高微处理器内核的资源利用率,是目前高性能微处理器研究的重点内容。
短句来源
更多       
  相似匹配句对
     core.
     内核
短句来源
     The Design of an Embedded CISC Microprocessor Core
     CISC微处理器嵌入式内核的设计
短句来源
     Advances in Power Supplies for Portable Microprocessor Core Voltages
     便携式微处理器内核电源电压的改进
短句来源
     the Pentium Microprocessor
     “奔腾”微处理器
短句来源
     Microprocessor & DSP
     微处理器与DSP
短句来源
查询“微处理器内核”译词为用户自定义的双语例句

    我想查看译文中含有:的双语例句
例句
为了更好的帮助您理解掌握查询词或其译词在地道英语中的实际用法,我们为您准备了出自英文原文的大量英语例句,供您参考。
  microprocessor core
The approach is illustrated on a simple out-of-order microprocessor core.
      
Most Systems-on-a-Chips include a custom microprocessor core, and time and resource constraints make the design of such devices a challenging task.
      
As seen in Chapter 11, automatic C-slowing of a microprocessor core can automatically create a multithreaded processor architecture.
      
Figure 3 shows the change in ED2 for the entire microprocessor core after exploiting slack.
      
It is done either by software in the microprocessor core or in specialized hardware in the FPGA.
      
更多          


It is not only helpful for making the problem small, accelerating the development speed through parallel development, and making the test easy, but also effective in solving some problems in digital VLSI design such as clock skew, power management, and so on. Some issues on the application of the divide-and-conquer strategy are concerned in this paper,furthermore, the design of OM80C51, an embedded microprocessor core, is presented as an example in which this strategy is applied. OM80C51 is compatible with 80C51....

It is not only helpful for making the problem small, accelerating the development speed through parallel development, and making the test easy, but also effective in solving some problems in digital VLSI design such as clock skew, power management, and so on. Some issues on the application of the divide-and-conquer strategy are concerned in this paper,furthermore, the design of OM80C51, an embedded microprocessor core, is presented as an example in which this strategy is applied. OM80C51 is compatible with 80C51. Some of its performances are better than those of 80C51. It provides shorter instruction cycles for most instructions, and some effective technologies are used in power management, and it has a customized interrupt system and periphery circuits.

文章讨论了分割取胜策略的优点和应用中的一些具体问题,并给出了设计实例,即微处理器内核OM80C51的设计。OM80C51是一个与80C51兼容但在性能上有一定改进的嵌入式微处理器内核

A new smart card chip architecture was developed with very high security for information security systems. The chip integrates an 8 bit microprocessor core, RSA cryptographic coprocessors and a large on chip Flash memory, together with memory access control logic and dedicated security circuits to improve the smart card's resistance against well known attacks, such as voltage/clock analysis and DPA (deferential power analysis) attacks. The architecture was implemented in 0.35 μm CMOS technology of TSMC....

A new smart card chip architecture was developed with very high security for information security systems. The chip integrates an 8 bit microprocessor core, RSA cryptographic coprocessors and a large on chip Flash memory, together with memory access control logic and dedicated security circuits to improve the smart card's resistance against well known attacks, such as voltage/clock analysis and DPA (deferential power analysis) attacks. The architecture was implemented in 0.35 μm CMOS technology of TSMC. The algorithm takes about 374 ms to complete a 1 024 bit RSA computation, so digital signatures and authentication are supported. The chip's high security and flexibility make it very suitable for use in electronic business systems, social security card systems and other fields.

为适应信息安全系统的要求 ,提出一种高安全性的智能卡芯片结构 ,并进行了设计实现。通过集成 8位微处理器内核、 RSA用加解密协处理器和大容量的片内 Flash存储器 ,以及存储器访问控制电路和专用的硬件安全电路 ,实现了系统的整体安全可靠性。该结构采用 TSMC公司0 .35 μm 的 CMOS工艺设计和制造 ,可以在 374 ms完成 10 2 4位 RSA运算 ,实现数字签名和身份认证 ,并能有效地防止非法操作、 DPA (deferential power analysis)分析等常见的攻击 ,适用于电子商务、社会保障卡系统等高安全性的应用领域

EC TM is the interface standard adopted by all MIPS RISC cores which implement the write-through protocols, and BIU(Bus Interface Unit) is one of the bus interface module in the high performance and low power 32 bit embedded CPU design. The paper presents a BIU interface circuit which is in accordance with EC TM protocol, and meets the demands of write-through. It emphasizes on introducing the function feature and time sequence feature of EC TM protocol, and also the general design scheme of BIU....

EC TM is the interface standard adopted by all MIPS RISC cores which implement the write-through protocols, and BIU(Bus Interface Unit) is one of the bus interface module in the high performance and low power 32 bit embedded CPU design. The paper presents a BIU interface circuit which is in accordance with EC TM protocol, and meets the demands of write-through. It emphasizes on introducing the function feature and time sequence feature of EC TM protocol, and also the general design scheme of BIU.

ECTM是所有执行通写策略的MIPS微处理器内核所采用的接口规范。而BIU(businter faceunit)是此次高性能、低功耗 32位嵌入式微处理器芯片设计中的一个总线接口模块 ,它是为了实现高速缓存 (cache)与外部存储器 (memory)之间的通写策略 (write through)而设计的一种总线接口单元。本文研究并设计了一种符合ECTM规范 ,且满足通写策略的BIU接口电路 ,并着重阐述了ECTM规范的功能特点、时序特征及BIU大致的设计方案。

 
<< 更多相关文摘    
图标索引 相关查询

 


 
CNKI小工具
在英文学术搜索中查有关微处理器内核的内容
在知识搜索中查有关微处理器内核的内容
在数字搜索中查有关微处理器内核的内容
在概念知识元中查有关微处理器内核的内容
在学术趋势中查有关微处理器内核的内容
 
 

CNKI主页设CNKI翻译助手为主页 | 收藏CNKI翻译助手 | 广告服务 | 英文学术搜索
版权图标  2008 CNKI-中国知网
京ICP证040431号 互联网出版许可证 新出网证(京)字008号
北京市公安局海淀分局 备案号:110 1081725
版权图标 2008中国知网(cnki) 中国学术期刊(光盘版)电子杂志社