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绝热逻辑
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  adiabatic logic
     However,it was faced with many difficulties to reduce the energy dissipation,so drew out adiabatic computing process. Through establishing the analytical model of power consumption in adiabatic logic,proven adiabatic logic circuit has the micro dissipation. Afterwards described the most common departures from true adiabatic in the logic designs that have been published to date,finally provides some design strategies for adiabatic logic designs in the future.
     从传统CMOS电路的能耗分析入手,在其面临难以降低功耗诸多困难的情况下,引出绝热逻辑的工作方式,建立了绝热逻辑的能耗分析模型,证明绝热逻辑是微功耗的.随后分析了目前诸多绝热逻辑设计中存在的一些问题,最后为今后的绝热逻辑设计提供了一些设计策略.
短句来源
  相似匹配句对
     Combinational Logic
     组合逻辑
短句来源
     True Degree Logic
     真度逻辑
短句来源
     Adiabatic Expansion of Electron Beam
     电子束的绝热展开
短句来源
     THE FOAMED PLASTICS USED IN CRYOGENIC INSULATION
     低温绝热泡沫塑料
短句来源
     Taking advantage of the adiabatic passage, this kind of quantum logic gate is robust against moderate fluctuations of experimental parameters.
     基于绝热演化的优点,这种量子逻辑门对实验参量的起伏不敏感.
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  adiabatic logic
A design philosophy of universal adiabatic logic gates is framed.
      
A computer simulation is carried out to investigate the power consumption of major quasi-adiabatic logic gates.
      
Design of two-phase sinusoidal power clock and clocked transmission gate adiabatic logic circuit
      
Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks-Clocked Transmission Gate Adiabatic Logic (CTGAL) circuit is presented.
      
Despite the plethoraof adiabatic logic architectures that have been proposed in recentyears, several practical considerations in the design of nontrivialadiabatic circuits remain largely unexplored.
      
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A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power...

A new low power quasi adiabatic logic,complementary pass transistor adiabatic logic (CPAL),is presented.The CPAL circuit is driven by a new three phase power clock,and its non adiabatic loss on output loads can be effectively reduced by using complementary pass transistor logic and transmission gates.Furthermore,the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors,thus it has more efficient energy transfer and recovery.A three phase power supply generator with a small control logic circuit and a single inductor is proposed.An 8 bit adder based on CPAL is designed and verified.With MOSIS 0 25μm CMOS technology,the CPAL adder consumes only 35% of the dissipated energy of a 2N 2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200MHz.

提出了一种由三相电源驱动的新绝热逻辑电路—— complementary pass- transistor adiabatic logic (CPAL ) .电路由 CPL电路完成相应的逻辑运算 ,由互补传输门对输出负载进行绝热驱动 ,电路的整体功耗较小 .指出选取合适的输出驱动管的器件尺寸可进一步减小 CPAL电路的总能耗 .设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路 .为了验证提出的 CPAL电路和时钟产生电路 ,设计了 8bit全加器进行模拟试验 .采用 MO-SIS的 0 .2 5μm CMOS工艺 ,在 5 0~ 2 0 0 MHz频率范围内 ,CPAL全加器的功耗仅为 PFAL电路和 2 N - 2 N2 P电路的 5 0 %和 35 % .

A new adiabatic logic circuit adopting two-phase non-overlap power clocks-Clocked Transmission Gate Adiabatic Logic circuit was designed by using the bootstrap effect of NMOS transistors,so that it could charge or discharge output loads in a fully adiabatic manner.Based on this circuit,a novel adiabatic SRAM was designed.So it could recover the charge of large switching capacitances on word-lines,write bit-lines,sense amplified lines and address decoders in a fully adiabatic manner.Using the parameters of TSMC...

A new adiabatic logic circuit adopting two-phase non-overlap power clocks-Clocked Transmission Gate Adiabatic Logic circuit was designed by using the bootstrap effect of NMOS transistors,so that it could charge or discharge output loads in a fully adiabatic manner.Based on this circuit,a novel adiabatic SRAM was designed.So it could recover the charge of large switching capacitances on word-lines,write bit-lines,sense amplified lines and address decoders in a fully adiabatic manner.Using the parameters of TSMC 0.25μm CMOS device,the adiabatic SRAM designed was simulated by HSPICE.The simulation results indicate that this SRAM has correct logic function and the character of clearly low power.

本文利用NMO S管的自举效应设计了一种新的采用二相无交叠功率时钟的绝热逻辑电路———钟控传输门绝热逻辑电路,实现对输出负载全绝热方式充放电.依此进一步设计了一种新型绝热SRAM,从而可以以全绝热方式有效恢复在字线、写位线、敏感放大线及地址译码器上的大开关电容的电荷.最后,在采用TSMC 0.25μm CMO S工艺器件参数情况下,对所设计的绝热SRAM进行HSPC IE模拟,结果表明,此SRAM逻辑功能正确,低功耗特性明显.

Started with power consumption analysis of the conventional CMOS circuit. However,it was faced with many difficulties to reduce the energy dissipation,so drew out adiabatic computing process. Through establishing the analytical model of power consumption in adiabatic logic,proven adiabatic logic circuit has the micro dissipation. Afterwards described the most common departures from true adiabatic in the logic designs that have been published to date,finally provides some design strategies for adiabatic logic...

Started with power consumption analysis of the conventional CMOS circuit. However,it was faced with many difficulties to reduce the energy dissipation,so drew out adiabatic computing process. Through establishing the analytical model of power consumption in adiabatic logic,proven adiabatic logic circuit has the micro dissipation. Afterwards described the most common departures from true adiabatic in the logic designs that have been published to date,finally provides some design strategies for adiabatic logic designs in the future.

从传统CMOS电路的能耗分析入手,在其面临难以降低功耗诸多困难的情况下,引出绝热逻辑的工作方式,建立了绝热逻辑的能耗分析模型,证明绝热逻辑是微功耗的.随后分析了目前诸多绝热逻辑设计中存在的一些问题,最后为今后的绝热逻辑设计提供了一些设计策略.

 
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