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逻辑波形
相关语句
  logical waveform
     The design of the revisable logical waveform generation circuit for color-PDP and its FPGA implementation
     彩色PDP可编辑的逻辑波形产生电路设计与实现
短句来源
     In this paper a revisable logical waveform generation circuit based on FPGA is presented with the use of this logical circuit combined with high-voltage driving circuit,and a revisable high-voltage pulse sequence generation circuit used in color-PDP is realized. Different PDP display panels can share the same circuit system so as to reduce the cost and cycle of research.
     采用max+plusII电路设计软件和FPGA实现可编辑的逻辑波形产生电路,与高压驱动电路相结合实现了可编辑的高压脉冲序列产生电路,使不同结构或同一结构不同参数的显示屏可以共享一套电路系统,降低PDP研发成本,缩短研发周期。
短句来源
  logic waveform
     Design and Implementation of a Logic Waveform Generation Circuit for Color-PDP
     彩色PDP逻辑波形产生电路的设计与实现
短句来源
     Logic waveform generator cicuit
     基于FPGA的彩色PDP逻辑波形产生电路
短句来源
  相似匹配句对
     Logic of Information Currents
     信息流逻辑
短句来源
     Fibring Logics
     纤维逻辑
短句来源
     replay of waveform data;
     波形回放;
短句来源
     Logic waveform generator cicuit
     基于FPGA的彩色PDP逻辑波形产生电路
短句来源
     Design and Implementation of a Logic Waveform Generation Circuit for Color-PDP
     彩色PDP逻辑波形产生电路的设计与实现
短句来源
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In this paper a revisable logical waveform generation circuit based on FPGA is presented with the use of this logical circuit combined with high-voltage driving circuit,and a revisable high-voltage pulse sequence generation circuit used in color-PDP is realized.Different PDP display panels can share the same circuit system so as to reduce the cost and cycle of research.The experiment indicates that this circuit using synchronization circuit design can generate a stable and reliable driving waveform.[

采用max+plusII电路设计软件和FPGA实现可编辑的逻辑波形产生电路,与高压驱动电路相结合实现了可编辑的高压脉冲序列产生电路,使不同结构或同一结构不同参数的显示屏可以共享一套电路系统,降低PDP研发成本,缩短研发周期。实验表明,采用同步电路设计的波形产生电路,工作稳定,输出波形光滑无“毛刺”。

A logic waveform generation circuit based on FPGA is presented By combining this circuit with a highvoltage driving circuit,a highvoltage pulse sequence generation circuit used in colorPDP is realized Results from experiment indicate that the circuitry using synchronous structure can generate a stable and reliable driving waveform,which can be readily modified,thus reducing the volume of memory and shorten the R & D cycle

 通过对波形数据存储方式的改进,利用现场可编程门阵列(FPGA)设计的逻辑波形产生电路,与高压驱动电路相结合,实现了彩色等离子体显示器(PDP)所需的高压脉冲序列波形。实验结果表明,采用同步设计的电路系统减少了波形的存储容量。该电路工作稳定可靠,输出的波形光滑无毛刺,而且可以很灵活地修改逻辑波形,从而降低了PDP研发成本,缩短了研发周期。

The digital logic analyzer is mainly used to analyze a set of logic signal waveforms in a digital system,and to show the logic relationship among them.In this paper,we use a Digital Signal Processor (DSP)to sample the eight channel digital signals,a CPLD to control the oscilloscope′s input electric circuit,and a dualport RAM to coordinate the data transformation between DSP and CPLD.The signals is sampled in the typical time segment according to the specified triggering condition.A state machine with 28 states...

The digital logic analyzer is mainly used to analyze a set of logic signal waveforms in a digital system,and to show the logic relationship among them.In this paper,we use a Digital Signal Processor (DSP)to sample the eight channel digital signals,a CPLD to control the oscilloscope′s input electric circuit,and a dualport RAM to coordinate the data transformation between DSP and CPLD.The signals is sampled in the typical time segment according to the specified triggering condition.A state machine with 28 states is designed in the CPLD to realize the digital channel display,time line display and trigging position display.It is convenient to analyze the logic relationships among the 8 digital signals,as they are displayed on the oscilloscope′s screen at the same time.This design can sample digital signals with the frequency up to 1 MHz.It allows users to set a 1~3 triggering condition levels.A further function development is allowed,too.All the above conforms this design to the need in digital system experiments and digital circuit design.This paper labors the software and hardware design and realization of this system.

逻辑分析仪主要功能是分析测量数字系统的逻辑波形和逻辑关系。该设计采用了一个DSP芯片对8路数字信号进行高速采样,一个CPLD芯片控制示波器接口电路,以及一个双口RAM协调DSP和CPLD之间数据传输。逻辑信号按照预先设计的触发条件在特定时间段内采集。在CPLD里设计了一个具有28个状态的状态机来实现数据通道显示、时间线显示和触发位置显示。8路数字信号同时在示波器显示屏上显示,可以让用户比较直观地分析8路数字信号的相对关系。该设计最高可采集的数字信号在1MHz左右,允许设置1~3级的触发条件,并可以进一步扩展功能,非常适合数字系统实验和数字电路设计的需要。详细分析和介绍了该系统的软硬件设计和实现。

 
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