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rtl验证
相关语句
  rtl verification
     RTL hybrid satisfiability solving is the key technique of RTL verification.
     RTL混合可满足性求解是RTL验证中的关键技术。
     Hybrid Satisfiability Solving for RTL Verification
     RTL验证中的混合可满足性求解
短句来源
  verification of rtl
     The design method is used for production of real chip after verification of RTL, software simulation based on ADS (ARM Developer Suit), and MPW (Multi project Wafer) project.
     该设计方法通过RTL验证,ADS(ARMDeveloperSuit)软件仿真,并通过MPW(Multi-ProjectWafer)的流片已生产出实际芯片。
短句来源
  “rtl验证”译为未确定词的双语例句
     RT-Level Verification Framework—HRV
     RTL验证框架——HRV
短句来源
     The experimen-tal results reveal that with the advantage of software modeling and software controlling technology,the process of our ASIC verification is obviously superior to the traditional process in condensing period,enhancing reliability and integrat-ing other evaluating environments.
     实验数据表明:由于采用软件模型和软件控制技术,该方案在缩短验证周期、提高验证可靠性、精确判定验证决策点以及有效集成各类验证环境等方面均明显优于传统RTL验证方案。
短句来源
     The experimental results reveal that with the advantage of software modeling and controlling technology, the process of our ASIC verification is obviously superier to the traditional process in condensing period, enhancing reliability and integrating other evaluating environments.
     实验数据表明:由于采用软件建模与控制技术,该方法在缩短验证周期、提高验证可靠性、精确判断验证程度以及有效集成各类验证环境等方面均明显优于传统RTL验证方法.
短句来源
  相似匹配句对
     RT-Level Verification Framework—HRV
     RTL验证框架——HRV
短句来源
     RTL Property Checking Based on Linear Programming
     基于线性规划的RTL性质验证研究
短句来源
     and D.
     在该机上验证了D.
短句来源
     validate the design.
     产品设计的验证;
短句来源
     Verilog RTL Model
     Verilog RTL模型
短句来源
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  rtl verification
RTL verification solution ensures that the SystemC-based architec ture models fit easily into a RTL design, enabling their use as reference models.
      
The model fulfills the RTL verification objective by reaching high simulation performances that are comparable to emulation capability.
      


This paper presents a RTL verification method in digital ASICs design based on SystemC modeling technolo-gy.The use of this method in an actual queue scheduler ASIC is also illustrated and analyzed in detail.The experimen-tal results reveal that with the advantage of software modeling and software controlling technology,the process of our ASIC verification is obviously superior to the traditional process in condensing period,enhancing reliability and integrat-ing other evaluating environments.

在分析当前数字专用集成芯片前端验证问题的基础上,提出了一种基于SystemC软件建模的专用集成芯片RTL级验证方法,并应用到对网络调度处理芯片的具体验证实验中。实验数据表明:由于采用软件模型和软件控制技术,该方案在缩短验证周期、提高验证可靠性、精确判定验证决策点以及有效集成各类验证环境等方面均明显优于传统RTL验证方案。

With respect to the verification bottleneck of current digital ASICs design, a RTL verification method is presented based on SystemC ASIC behavior modeling and test controlling technology. The use of this method in an actual queue scheduler ASIC is also illustrated and analyzed for detail. The experimental results reveal that with the advantage of software modeling and controlling technology, the process of our ASIC verification is obviously superier to the traditional process in condensing period, enhancing...

With respect to the verification bottleneck of current digital ASICs design, a RTL verification method is presented based on SystemC ASIC behavior modeling and test controlling technology. The use of this method in an actual queue scheduler ASIC is also illustrated and analyzed for detail. The experimental results reveal that with the advantage of software modeling and controlling technology, the process of our ASIC verification is obviously superier to the traditional process in condensing period, enhancing reliability and integrating other evaluating environments.

针对当前数字专用集成电路设计中的验证瓶颈,提出了一种基于SystemC电路行为建模与测试控制技术的专用集成电路验证方法,并应用到网络调度芯片的具体验证实验中.实验数据表明:由于采用软件建模与控制技术,该方法在缩短验证周期、提高验证可靠性、精确判断验证程度以及有效集成各类验证环境等方面均明显优于传统RTL验证方法.

Taking information system as the target, SoC can save the resources of software and chip greatly, meanwhile the degree of system integration and the performance to price ratio can also be improved significantly by directly optimizing software and hardware (embedded software and chip’s architecture). This paper explains the optimized design of MP3 subsystem in SoC oriented to multimedia basing on ARM7TDMI. Multimedia accelerator module (MMA), on-chip SRAM and the related software optimization scheme are used...

Taking information system as the target, SoC can save the resources of software and chip greatly, meanwhile the degree of system integration and the performance to price ratio can also be improved significantly by directly optimizing software and hardware (embedded software and chip’s architecture). This paper explains the optimized design of MP3 subsystem in SoC oriented to multimedia basing on ARM7TDMI. Multimedia accelerator module (MMA), on-chip SRAM and the related software optimization scheme are used in our SoC, leading to a SoC design method oriented to multimedia application based on low end RISC processor core. The design method is used for production of real chip after verification of RTL, software simulation based on ADS (ARM Developer Suit), and MPW (Multi project Wafer) project. Moreover, the result obtained the expected effect which is shown by the verification of actual chip prototype demo.

以信息系统作为目标直接优化软、硬件的片上系统(SoC)将大大节省软件和芯片资源,大大提高系统的集成度和性价比。文中主要介绍基于ARM7TDMI的面向多媒体的SoC中MP3子系统的优化设计。通过在SoC中增加多媒体加速器(MMA)模块和片上SRAM以及相关的软件优化方案,提出了一种基于低端精简指令集计算机(RISC)处理器核的面向多媒体应用(MP3)的SoC设计方法。该设计方法通过RTL验证,ADS(ARMDeveloperSuit)软件仿真,并通过MPW(Multi-ProjectWafer)的流片已生产出实际芯片。在实际的芯片样机上得到了验证,达到了设计效果。

 
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