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时钟倍频器
相关语句
  clock multiplier
     The clock multiplier provides the SDRAM, and it's controller module with a triple- frequency clock which features zero delay.
     时钟倍频器在系统中可以为SDRAM及其控制模块提供与其它时钟同相位的高频时钟。
短句来源
  “时钟倍频器”译为未确定词的双语例句
     Design of a High-speed Frequency Multiplier Used in 2.5 Gbps Ethernet Transceiver
     用于2.5Gbps千兆以太网发接器的时钟倍频器设计
短句来源
     Design of a PLL Clock Frequency Multiplier for LVDS Driver
     一种用于LVDS驱动器的PLL时钟倍频器的设计
短句来源
     Phase-Locked Loop (PLL), which works as a clock synthesizer, has become a necessary and core part in modern microprocessors. It works on the top of the clock tree.
     锁相环(Phase-Locked Loop,PLL)电路作为时钟倍频器已经成为当代微处理器必不可少的核心组成部件。
短句来源
     A high speed PLL frequency multiplier used in 2.5 Gbps et hernet transceiver is designed.
     提出了一种电荷泵锁相环电路实现的适用于 2 .5Gbps千兆以太网发接器要求的高速时钟倍频器的设计方法。
短句来源
  相似匹配句对
     The clock sings
     时钟的歌唱
短句来源
     Study on Frequency Multiplier
     倍频器的研究
短句来源
     Design of a PLL Clock Frequency Multiplier for LVDS Driver
     一种用于LVDS驱动器的PLL时钟倍频器的设计
短句来源
     An 18GHz Multiplier
     18千兆赫倍频器
短句来源
     CIRCUITS FOR PROGRAMMABLE CLOCK GENERATORS
     可编程的时钟发生器
短句来源
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  clock multiplier
An internal PLL clock multiplier is included and generates the necessary on-chip high frequency clocks.
      
Finally, he proved through simulation that digital phase-locked-loops could be used in order to improve the clock multiplier's response to jitter.
      
For example, an M value of 19 and a D value of 8 yields a 2.375 source clock multiplier.
      
This device receives clock rate input from the main board, and generates a divided clock output which is then output to a clock multiplier device.
      
The SFDR specification is achieved with the low-jitter clock multiplier circuitry enabled.
      
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A high speed PLL frequency multiplier used in 2.5 Gbps et hernet transceiver is designed.By using dual delay scheme to implement VCO and u sing dynamic D flip flop to implement fr equency divider,high operation frequency is achieved.In addition,a temperature c ompensation technique in VCO is adopted to obtain low temperature sensitivity an d the unity gain amplifier is added in c harge pump to avoid the charge sharing e rror.By using UMC 0.18 μm, 1.8 V CMOS t echnology and spectreS simulator in...

A high speed PLL frequency multiplier used in 2.5 Gbps et hernet transceiver is designed.By using dual delay scheme to implement VCO and u sing dynamic D flip flop to implement fr equency divider,high operation frequency is achieved.In addition,a temperature c ompensation technique in VCO is adopted to obtain low temperature sensitivity an d the unity gain amplifier is added in c harge pump to avoid the charge sharing e rror.By using UMC 0.18 μm, 1.8 V CMOS t echnology and spectreS simulator in Cade nce environment,the results show that th is PLL frequency multiplier can meet the requirements of the system under differ ent PVT(Many circuit parameters vary wit h the fabrication process,supply voltage ,and ambient temperature,and we denote t hese effects by PVT),and even in the wor st case the circuit can keep a good phas e jitter performance.The static phase er ror between input and output is 50 ps an d the whole circuit dissipates 35 mW on the average.

提出了一种电荷泵锁相环电路实现的适用于 2 .5Gbps千兆以太网发接器要求的高速时钟倍频器的设计方法。为了获得高速时钟 ,设计中采用了双环路的 VCO结构 ,并且运用动态 D触发器来实现高速分频器。同时为了使得 PLL性能更加稳定 ,对电路作了进一步改进 :在 VCO的延迟单元中加了温度补偿部分 ,又采用箝位技术消除电荷泵中电荷重新分配引入的影响。运用 UMC0 .18μm,1.8V CMOS工艺模型 ,在 Cadence的环境下用 spectre S仿真器模拟 ;结果表明设计的时钟倍频电路对于不同的 PV T( P表示工艺变化引起的模型参数的变化 ,VT表示系统工作条件温度和电源电压的变化 )均能得到符合满足 2 .5Gbps千兆以太网发接器要求的时钟倍频信号 ,即使在最坏情况下电路也能保持很好的相位跟踪特性 ,输出静态相位误差平均为 50 ps,整个电路的功耗平均为 35m W。

A kind of real-time system which designed for distortion-correction in wide angle lens is introduced. A certain algorithm is used to get the proper vertical coordinate and horizontal coordinate of every pixel according to the analysis of distortion.The implementing method and the circuits are also shown. By taking the FPGA as the key component, the system combined with the digital video encoder and decoder can eliminate the image distortion. The clock multiplier provides the SDRAM, and it's controller module...

A kind of real-time system which designed for distortion-correction in wide angle lens is introduced. A certain algorithm is used to get the proper vertical coordinate and horizontal coordinate of every pixel according to the analysis of distortion.The implementing method and the circuits are also shown. By taking the FPGA as the key component, the system combined with the digital video encoder and decoder can eliminate the image distortion. The clock multiplier provides the SDRAM, and it's controller module with a triple- frequency clock which features zero delay.

介绍了一种广角镜头图像畸变的实时校正系统。通过对光学系统畸变原理的分析,采用一定的算法对像素空间的位置进行几何变换,减少了由镜头大视场带来的几何畸变。整个系统以FPGA为核心控制器件,结合数字图像编码解码芯片和SDRAM存储器,可实现视频图像的实时校正。时钟倍频器在系统中可以为SDRAM及其控制模块提供与其它时钟同相位的高频时钟。

 
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