助手标题  
全文文献 工具书 数字 学术定义 翻译助手 学术趋势 更多
查询帮助
意见反馈
   应变硅 的翻译结果: 查询用时:0.054秒
图标索引 在分类学科中查询
所有学科
无线电电子学
更多类别查询

图标索引 历史查询
 

应变硅     
相关语句
  strained si
     90nm technology consists of193nm lithography technology,high k insulating material,high speed Cu interconnection technology,low k insulating material,strained Si technology and voltage isolation technology etc.
     90nm工艺包括193nm光刻技术、高k绝缘材料、高速多层铜互连技术、低k绝缘材料、应变硅技术和电压隔离技术等新技术。
短句来源
     (3) Epitaxy of strained Si on the obtained SGOI substrate.
     (3)在获得的SGOI衬底材料上生长高质量应变硅材料。
短句来源
     In strained-Si PMOSFET with Si0.76Ge0.24 substrate, the mobility enhancement factor is 1.25. However, as the Ge content in SiGe substrate surpasses 40%, the mobility enhancement in strained Si PMOSFET becomes saturated.
     对于衬底中Ge含量为24%的应变硅PMOSFET,空穴迁移率是相同尺寸硅PMOSFET的1.25倍,当Ge含量超过40%时,空穴迁移率达到饱和。
短句来源
     An investigation is made into preparations of thin gate-oxides for strained Si channel MOSFET's using PECVD at 300 °C and low-temperature (700-800 °C) thermal oxidation, respectively.
     分别对300°C下采用等离子体增强化学气相淀积(PECVD)和700°C下采用热氧化技术制备应变硅沟道MOS器件栅介质薄膜进行了研究。
短句来源
     Strained Si technology, SOI (Silicon-on-lnsulator) technology and high K dielectric materials which are hatched from the tremendous success of today's IC industry can provide some of the solutions in the sub-100-nm technology node.
     应变硅技术、SOI(Silicon-on-Insulator)技术和高K栅介质材料是三项在硅材料与硅集成电路巨大成功的基础上出现的,有独特优势、能突破体硅材料与硅集成电路限制的新兴技术。
短句来源
更多       
  strained silicon
     The 45 nm main technology includes lithography, strained silicon, low-k dielectric, Cu interconnection, high-k dielectric and ion implantation etc.
     45nm主要工艺包括光刻、应变硅、低k电介质、Cu互连、高k电介质和离子注入等。
短句来源
     The 300mm wafer and the 90nm new technology contains the 193nmphotolithography,the Cu interconnection , the low-k insulating Layer , the CMP, the high-kinsulating layer, the strained silicon and SOI etc .
     300mm晶圆与90nm工艺是互动的。 90nm新工艺主要包括193nm光刻技术、铜互连、低k绝缘层、CMP、高k绝缘层、应变硅和SOI等。
短句来源
     The ITRS2001demands that the IC chip feature size achieves90nm in the year2004.In or-der to realize the ITRS2001,the many new technology of IC manufacturring must be used,such as the Cu interconnection,the low-k insulating layer,the CMP,the high-k insulating layer,the strained silicon and SOI etc.
     2001《国际半导体技术指南(ITRS)》要求2004年IC芯片特征尺寸达90nm。 为了实现这个规划,必须采用IC制造的多种新工艺,如铜互连、低k绝缘层、CMP、高k绝缘层、应变硅和SOI等。
短句来源
     SGOI (SiGe on Insulator) and SGOI-based sSOI (Strained Silicon on Insulator) have the advantages of both SiGe and SOI technologies. In recent years, SGOI, which is listed in the International Technology Roadmap for Semiconductors, has attracted more and more attentions and become the focus of research activities in microelectronic materials, leading to further development of Si-based IC's.
     绝缘体上的锗硅技术(SiGe on Insulator,SGOI)和以它为衬底开发的应变硅技术 (Strained Silicon on Insulator,sSOI)融合了SiGe技术和SOI技术二者的优点,是近年来人们广泛 重视的研究热点和硅基集成电路产业进一步发展的重要研究方向,是国际半导体技术发展路线图 (ITRS)中CMOS技术今后几年发展的方向。
短句来源
     To construct the threshold voltage model for the surface-channel strained silicon N/P MOSFETs and quantum mechanical SiGe-channel PMOSFETs , physics-based short-channel threshold voltage models are given on this paper.
     然后采用电压-杂质变换的方法,将应变硅表面沟道N/P MOSFFET和量子SiGe沟道PMOSFET的阈值电压模型拟合到传统的长沟道阈值电压模型中,充分利用了长沟道阈值电压模型的简洁性。
短句来源
更多       
  strained-si
     k·p and Monte Carlo Studies of Hole Mobility in Strained-Si pMOS Inversion Layers
     应变硅pMOS反型层中空穴迁移率k·p及蒙特卡罗模拟研究
短句来源
     Both the theoretical simulation and experiment results show that the relationship betweenμeff and Eeff in strained-Si is similar to the one in bulk Si. The mobility reaches its maximum when Eeff equals to 2×105V/cm.
     理论分析和实验结果表明,应变硅载流子迁移率与横向电场Eeff的函数关系与体硅材料类似,峰值迁移率所对应的Eeff为2×105V/cm。
短句来源
     In strained-Si PMOSFET with Si0.76Ge0.24 substrate, the mobility enhancement factor is 1.25. However, as the Ge content in SiGe substrate surpasses 40%, the mobility enhancement in strained Si PMOSFET becomes saturated.
     对于衬底中Ge含量为24%的应变硅PMOSFET,空穴迁移率是相同尺寸硅PMOSFET的1.25倍,当Ge含量超过40%时,空穴迁移率达到饱和。
短句来源
     In order to design strained-Si MOSFETs more efficiently, it is necessary to thoroughly analysis the mechanism behind mobility enhancement and thus establish related model to clarify the relationship between mobility and strain.
     为了更有效的设计、应用应变硅MOSFET,必须深入研究应变硅中载流子的迁移率增强机理,并在此基础上建立相应的物理模型,导出应力强度与迁移率的定量关系。
短句来源
  “应变硅”译为未确定词的双语例句
     epitaxial Si1-xGex/Si system may also be used in many new device architectures at these days, such as strained Si-CMOS devices, modified doping field effect transistor(MODFET), quantum well metal-oxide-semiconductor field effect transistor(QWMOSFET),etc.
     外延Si_(1-x)Ge_x/Si系统在某些新型器件结构,如应变硅(strained Si)CMOS器件,调制掺杂场效应晶体管(MODFET),量子阱金属-氧化物-半导体场效应晶体管(QWMOSFET)等也可能得到应用。
短句来源
     The hole mobility dependence on the transverse electric field for both uniaxial compression and biaxial tension is studied with the Monte Carlo method and compared with the case of unstrained silicon.
     采用蒙特卡罗方法对单轴压应力和双轴张应力情况下的空穴迁移率进行了模拟研究,得出了沟道迁移率随垂直于沟道电场变化的曲线,并与常规的非应变硅pMOS迁移率进行了比较.
短句来源
     Research on Relaxation of SiGe/SOI and Fabrication of SSOI Materials
     SOI基锗硅弛豫研究及绝缘体上应变硅材料制备
短句来源
     Preparation of Low-Temperature SiO_2 Gate Insulators for Strained Si-Channel Heterojunction PMOSFET's
     低温制备应变硅沟道MOSFET栅介质研究
短句来源
     Using polynomial Parameter fitting, low-field enhance factor model of the strained MOSFETs is constructed ,which makes it possible to directly use the model in pspice ;
     迁移率低场增强因子模型的建立使得应变硅MOSFET可以直接使用硅MOSFET的迁移率模型,如PSPICE BSIMV3中的相关模型,为应变硅VLSI电路模拟提供了一条捷径。
短句来源
查询“应变硅”译词为用户自定义的双语例句

    我想查看译文中含有:的双语例句
例句
为了更好的帮助您理解掌握查询词或其译词在地道英语中的实际用法,我们为您准备了出自英文原文的大量英语例句,供您参考。
  strained si
It is found that the nonuniform spatial elastic strain distribution in this medium gives rise to a three-dimensional potential well for electrons in the strained Si layers near Ge nanoclusters.
      
The existence of bound electron states in the conduction band of strained Si must lead to a relaxation of the selection rules that determine the low efficiency of the radiative recombination in indirect-gap semiconductors.
      
The growth of self-assembled Ge(Si) islands on a strained Si1-xGex layer (0% >amp;lt; x >amp;lt; 20%) is studied.
      
Special features of the photoluminescence of self-assembled Ge(Si)/Si(001) islands grown on a strained Si1-xGex layer
      
The effect of the predeposition of strained Si1 - xGex layers (x ≤ 20%) on photoluminescence (PL) of self-assembled Ge(Si)/Si(001) islands is studied.
      
更多          
  strained silicon
Spectral characteristics of linear dichroism in uniaxially-strained silicon crystals in the region of edge absorption were studied using the polarization-modulation technique.
      
The final set of simulations deals with the interaction of water with a crack in strained silicon.
      
Hole Transport in Orthorhombically Strained Silicon
      
Phonon Scattering Effects on Temperature Dependence of Conductivity in Strained Silicon
      
Temperature dependence on conductivity in strained silicon is simulated.
      
更多          
  strain si
herbarum, Fusarium chlamydosporum, Penicillium simplicissimum and P.restrictum strains I and II.
      
The South Indian strain (SI) is most variable and measures of genetic distance set it apart from the other strains.
      
Using a QCM-setup we investigated the time course of cell attachment and spreading as a function of seeding density for three widespread and frequently used cell lines (MDCK strains I and II and Swiss 3T3-fibroblasts).
      
Strains I2 and I8 independently formed single-culture aerobic granules except for I3.
      
Anti-microbial activity test results indicated that strains I2 and I8 inhibited growth of strain I3.
      
更多          
  strained-si
Strained-Si/SiGe heterostructure is studied by EBIC.
      
Fabrication of strained-Si channel p-MOSFET's on ultra-thin SiGe virtual substrates
      
In the ultra-thin relaxed SiGe virtual substrates, a strained-Si channel p-type Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) is presented.
      
Built on strained-Si/240nm relaxed-Si0.8 Ge0.2/100nm Low Temperature Si (LT-Si)/10nm Si buffer was grown by Molecular Beam Epitaxy (MBE), in which LT-Si layer is used to release stress of the SiGe layer and made it relaxed.
      
Measurement indicates that the strained-Si p-MOSFET's (L-4.2 μm) transconductance and the hole mobility are enhanced 30% and 50% respectively, compared with that of conventional bulk-Si.
      
更多          


The band offset between strained Ge_xSi(1-x)and unstrained Si is mainly due to the valence band offset ΔE_v. The thermal emission energy from a quantum well is related to the appropriate band offset. The single quantum well (p type Si/Ge(0.25)Si(0.75)/Si) samples were grown by molecular beam epitaxy (MBE), the width of quantum well is 15nm. Deep leve transient spectroscopy (DLTS) measurement have been used to study the valence band offset. After considering the band bending due to the electric field and the...

The band offset between strained Ge_xSi(1-x)and unstrained Si is mainly due to the valence band offset ΔE_v. The thermal emission energy from a quantum well is related to the appropriate band offset. The single quantum well (p type Si/Ge(0.25)Si(0.75)/Si) samples were grown by molecular beam epitaxy (MBE), the width of quantum well is 15nm. Deep leve transient spectroscopy (DLTS) measurement have been used to study the valence band offset. After considering the band bending due to the electric field and the first subband energy, the valence band offset ΔEv of the single quantum well was estimated as about 0.19eV, it is in reasonable agreement with theoretical results. The same and difference of emission and capture processess between quantum well and deep level defects were discussed.

应变的Ge_xSi_(1-x)层和未应变的硅层间的能带偏移主要是价带偏移。量子阱中载流子的热发射能与界面的能带偏移有着密切的关系。本文用深能级瞬态谱(DLTS)研究分子束外延生长的p型Si/Ge_(0.25)Si_(0.75)/Si单量子阱的价带偏移,阱宽为15nm,考虑到电场的影响和量子阱中第一子能级的位置,对从DLTS得到的热发射能进行适当的修正,可以计算出Si/Ge_(0.25)Si_(0.75)/Si的价带偏移为0.19eV,与理论值符合尚好。本文还讨论了量子阱中载流子的发射、俘获过程与深能级陷阱中载流子的发射、俘获过程之间的异同。

The ITRS2001planned that in2004the90nm technology would be realized.In2003,Intel,AMD etc.semiconductor companies will adopt the90nm technology for batch pro-cess in MPU and logical device.Thus the ITRS Plan2001is one year ahead of time.90nm technology consists of193nm lithography technology,high k insulating material,high speed Cu interconnection technology,low k insulating material,strained Si technology and voltage isolation technology etc.193nm photolithography is the key technology for90nm batch process,so193nm...

The ITRS2001planned that in2004the90nm technology would be realized.In2003,Intel,AMD etc.semiconductor companies will adopt the90nm technology for batch pro-cess in MPU and logical device.Thus the ITRS Plan2001is one year ahead of time.90nm technology consists of193nm lithography technology,high k insulating material,high speed Cu interconnection technology,low k insulating material,strained Si technology and voltage isolation technology etc.193nm photolithography is the key technology for90nm batch process,so193nm ArF step per must be used in this process.In this paper,the problems of90nm technology mass production are introduced,such as the cost of mask is relatively high,the yield is relatively low and the range of application is relatively narrow etc.

ITRS2001规划2004年实现90nm工艺,英特尔、AMD等世界顶级半导体公司将于2003年采用90nm工艺量产微处理器和逻辑器件。这样使ITRS2001整整提前了一年。90nm工艺包括193nm光刻技术、高k绝缘材料、高速多层铜互连技术、低k绝缘材料、应变硅技术和电压隔离技术等新技术。193nm光刻技术是实现90nm工艺达量产的最关键技术,为此,必须采用193nmArFstepper(准分子激光扫描分步投影光刻机)。讨论了90nm工艺达量产的难点,如掩模版成本较高、成品率较低和应用面暂时不宽等。

The most updated90nm manufacturing technology is introduced,along with some new techniques such as strained silicon and50nm gate-length transistor.Finally a prospect about the development of IC in the future is made.

介绍集成电路制造技术90nm最新工艺的一些动态及采用的新技术,如应变硅、50nm晶体管栅极长度,并对今后集成电路的发展做了简单展望。

 
<< 更多相关文摘    
图标索引 相关查询

 


 
CNKI小工具
在英文学术搜索中查有关应变硅的内容
在知识搜索中查有关应变硅的内容
在数字搜索中查有关应变硅的内容
在概念知识元中查有关应变硅的内容
在学术趋势中查有关应变硅的内容
 
 

CNKI主页设CNKI翻译助手为主页 | 收藏CNKI翻译助手 | 广告服务 | 英文学术搜索
版权图标  2008 CNKI-中国知网
京ICP证040431号 互联网出版许可证 新出网证(京)字008号
北京市公安局海淀分局 备案号:110 1081725
版权图标 2008中国知网(cnki) 中国学术期刊(光盘版)电子杂志社