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rtl仿真
相关语句
  rtl simulation
     When block level verification reaches the required domain and functional coverage, the C based SoC chip level verification method is used to verification whole chip, results show that whole chip can be verified at speed of 20 times of Verilog RTL simulation.
     模块验证达到所需要的域和功能覆盖率后,SoC验证重点转向芯片级(Chip-Level)验证,采用基于C建模的SoC芯片级验证方法验证整个芯片功能,数据结果表明该方法比传统的RTL仿真速度提高了20倍以上。
短句来源
     4.The RTL simulation of the CLB-PVCI bridge.
     4.CLB-PVCI桥的RTL仿真
短句来源
     The digital IC design flow and methodology based on standard cell library is presented The digital IC design flow begins with behavioral HDL descriptions, followed by system behavioral simulation, behavioral synthesis, RTL simulation, logic synthesis, post synthesis simulation, auto planning and routing, post layout simulation Finally, the interrelation between physical design and logic design is dealt with
     数字集成电路设计流程从行为级的 HDL描述开始 ,依次进行系统行为级仿真 ,行为级综合 ,RTL仿真 ,逻辑综合 ,综合后仿真 ,自动化布局布线 ,版图后仿真等步骤。 讨论了如何把物理设计环境和逻辑设计环境联系起来 ,以解决物理设计和逻辑设计相脱节的问题
短句来源
     A programmable direct memory access (PDMA) control module is designed. As a softIP core, it is used to establish a kind of PCI protocol-based FPGA hardware verification platform,after RTL simulation, synthesis, implement and download to a FPGA with PCI IP core.
     设计了一种用于测试SDRAM的可编程直接存储器存取控制模块(PDMA),把设计的PDMA作为IP软核,在基于PCI环境的RTL仿真平台上进行功能仿真、综合并将结果下载到PFGA上,建立基于FPGA的测试平台进行硬件测试验证。
短句来源
  “rtl仿真”译为未确定词的双语例句
     ICT-godson has the same logic behavior with the Godson-2 RTL model, but it can run 10x faster.
     ICT-godson和RTL的逻辑行为相同,但速度可以比RTL仿真高一个数量级以上。
短句来源
     The result of the RTL
     最终的RTL仿真结果表明,
短句来源
     The project was designed according to the procedure from top to bottom, including dividing module , writing codes , RTL emulation , synthesizes from system , placement and routing , get to FPGA and realize.
     这个项目按照自上而下的设计流程,从系统划分、编写代码、RTL仿真、综合、布局布线,到FPGA实现。
短句来源
     This passage discusses input and output signals of various modules and their corresponding relations,and it also describes each module by using hardware description language and make RTL imitation.
     本文从定时器的功能要求入手,首先讨论了各个模块的输入和输出信号及其模块间的信号对应关系,然后采用EDA的方式,利用硬件描述语言对各个模块进行描述,并进行RTL仿真
短句来源
     In microprocessor validation,dynamic simulation based verification is the dominant methodology.
     基于动态的RTL仿真依然是验证超大规模集成电路的主要方法。
短句来源
  相似匹配句对
     The result of the RTL
     最终的RTL仿真结果表明,
短句来源
     4.The RTL simulation of the CLB-PVCI bridge.
     4.CLB-PVCI桥的RTL仿真
短句来源
     Simulation System for Ship Navigate
     船舶驾驶仿真
短句来源
     LAN emulation over ATM
     局域网仿真
短句来源
     Verilog RTL Model
     Verilog RTL模型
短句来源
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  rtl simulation
After the validation of the virtual architecture and the generation of RTL architecture as shown in Figure 1, we generated an RTL simulation model.
      
A program was also written to compare the Scanout data with RTL simulation to aid in interpreting the data.
      
Later, RTL simulation is performed to verify the hypothesis made based on the collected data and to identify the failing node.
      
Not only the FPGA board verifies the same behavior in RTL simulation, but also directly performs recognition experiments via a microphone.
      
RTL simulation was used to validate the remaining assertions based on the given set of test cases.
      
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The digital IC design flow and methodology based on standard cell library is presented The digital IC design flow begins with behavioral HDL descriptions, followed by system behavioral simulation, behavioral synthesis, RTL simulation, logic synthesis, post synthesis simulation, auto planning and routing, post layout simulation Finally, the interrelation between physical design and logic design is dealt with

介绍了基于标准单元库的数字集成电路设计流程和方法学。数字集成电路设计流程从行为级的 HDL描述开始 ,依次进行系统行为级仿真 ,行为级综合 ,RTL仿真 ,逻辑综合 ,综合后仿真 ,自动化布局布线 ,版图后仿真等步骤。讨论了如何把物理设计环境和逻辑设计环境联系起来 ,以解决物理设计和逻辑设计相脱节的问题

A programmable direct memory access (PDMA) control module is designed. As a softIP core, it is used to establish a kind of PCI protocol-based FPGA hardware verification platform,after RTL simulation, synthesis, implement and download to a FPGA with PCI IP core. The hard-ware test result shows this PDMA core achieve the design goal for fast access with work fre-quency over 66MHz. PDMA emulates the data exchange between many IPs and SDRAM simulta-neously by using the general PCI environment. So this design can...

A programmable direct memory access (PDMA) control module is designed. As a softIP core, it is used to establish a kind of PCI protocol-based FPGA hardware verification platform,after RTL simulation, synthesis, implement and download to a FPGA with PCI IP core. The hard-ware test result shows this PDMA core achieve the design goal for fast access with work fre-quency over 66MHz. PDMA emulates the data exchange between many IPs and SDRAM simulta-neously by using the general PCI environment. So this design can be used to verify many differentcooperating IP cores at the same time, which shall be an effective and important solution for IPdevelopment. It also shortens the time-to-market of the IP product, and especially is meaningfulfor soft IP core development.

设计了一种用于测试SDRAM的可编程直接存储器存取控制模块(PDMA),把设计的PDMA作为IP软核,在基于PCI环境的RTL仿真平台上进行功能仿真、综合并将结果下载到PFGA上,建立基于FPGA的测试平台进行硬件测试验证。结果表明,板上PDMA工作频率66MHz,达到快速访问的设计要求。PDMA仿真了多个IP与SDRAM的数据交换,并且建立在通用的PCI环境下。因此本设计方法和建立的仿真测试环境可用于不同的IP,是解决不同IP开发中十分重要的仿真测试方案,大大缩短了IP开发的测试和验证的时间,对于发展IP软核有重要意义。

This paper presents an OCP-communication based hw/sw co-modeling method in the SoC virtual component level design By the method, we create a virtual component level model—FITM(Function Interface-Timing Model) The virtual component level's model acts between system level's algorithm model and RTL's cycle accurate model, to simplify the mapping from system level's task to RTL's architecture FITM-based co-simulation can compromise the accuracy and speed of co-simulation, to effectively solve the problem...

This paper presents an OCP-communication based hw/sw co-modeling method in the SoC virtual component level design By the method, we create a virtual component level model—FITM(Function Interface-Timing Model) The virtual component level's model acts between system level's algorithm model and RTL's cycle accurate model, to simplify the mapping from system level's task to RTL's architecture FITM-based co-simulation can compromise the accuracy and speed of co-simulation, to effectively solve the problem that system level's simulation is not accurate enough and RTL's simulation is too slow The result from co-simulation can support the decision of hw/sw partition and the analysis of the SoC system's performance In order to make the hw/sw model in the virtual component level independent of RTL's bus protocol, we use the open core protocol's transaction communication protocol, to substantially improve the reusability of the model Finally, the FITM of Digital Soldier Audio/Video Decoder SoC is demonstrated

提出了一种基于OCP(OpenCoreProtocol)通信协议的虚部件级软硬件协同建模方法 ,并建立虚部件级模型———FITM (FunctionInterfaceTimingModel) FITM介于系统级算法模型和RTL时钟精确的模型之间 ,可简化系统级任务直接映射到RTL体系结构的难度 ;基于FITM的协同仿真对仿真的精确性和速度进行折中 ,可有效地解决系统级仿真不够精确和RTL仿真速度慢的问题 ,所得到的仿真结果能最佳地支持软硬件划分决策和系统性能分析 为了使虚部件级软硬件模型之间的通信独立于RTL的总线协议 ,文中采用OCP事务级通信协议 ,大大提高了模型的重用性 最后给出MP3Decoder和数字化士兵音视频解码与播放器SoC的建模实例

 
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