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rtl设计
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  rtl design
     The work of this dissertation is to complete the RTL design and verification of CLB-PVCI bus bridge after studying and analyzing the CLB bus protocol and PVCI protocol.
     本论文工作就是在研究和分析CLB总线协议和PVCI协议的基础上,完成CLB-PVCI总线桥的RTL设计和验证。
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     This paper then analysis the redundant information in Verilog RTL design, introducing a new Vperl2 syntax for FSM design automation.
     本文对Verilog RTL设计中的冗余信息进行了较为深入的分析,针对有限状态机设计冗余引入了新的Vperl2语法。
短句来源
     The studying here just limited in the conversion from system design to RTL design, regardless of how to do RTL design, verification and even the co-design of software and hardware with SystemC.
     这里仅限于对系统设计部分以及系统设计向RTL设计的转换,并不涉及SystemC的RTL设计,验证以及软硬件协同设计方面的研究。
短句来源
     Vperl can eliminate the Verilog redundancy, through automatic IO port deducing, automatic sensitivity list completion and automatic inter-module wire connect, greatly improve RTL design efficiency.
     Vperl是一种Verilog预处理工具,通过自动生成输入输出端口列表、模块自动互连等等方式让设计者可以专注于逻辑实现,从而大幅度提高了VLSI前端RTL设计效率。
短句来源
     The second chapter presents encoder and decoder RTL design, as well as parallel interleaver/deinterleaver design based on multi-port memory.
     第二章为基于帧分裂和归零的并行Turbo编码的设计与实现,分别介绍了编码器和译码器的RTL设计,还提出了一种基于多端口存储器的并行子交织器和解交织器设计。
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  “rtl设计”译为未确定词的双语例句
     Using the new flow, we get high efficiency of hardware design and high reliability of system verification.
     采用新的流程克服了又有流程系统设计和RTL设计分裂而造成的种种弊端,既简化了设计流程,又增加了验证的可靠性,提高了验证效率。
短句来源
     Instead of using C-to-Verilog flow, we use SystemC to be the only language to descript the system to RTL level design.
     在硬件设计方面,本文打破了原有的C2Verilog设计流程,采用了SytemC语言进行系统验证和RTL设计
短句来源
     Meanwhile, when researching the above method, we find that ifhierarchical module structure of RTL designs would be added intoverification process, the high performance must be obtained.
     在进行上述技术研究时,我们发现如果能够将RTL设计的模块化层次式结构信息引入到验证系统中来,将对验证过程起到较大的指导意义。
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     Wedevelop further H-LPSAT using this strategy and deal with hierarchicalRTL designs.
     我们进一步开发了H-LPSAT系统。 它可以验证层次式的RTL设计
短句来源
     In the later, we hope to establish a practical platform based on the above work and find out a new way to use SystemC effectively in the system design of IP Core design field and conversion to RTL, shorten the design circle and promote efficiency.
     在今后的工作中,希望能够在此基础上形成一套适合于实际情况使用的利用SystemC这个新的系统级描述语言在IP核设计过程中进行系统设计以及向RTL设计转换的方法,有效的缩短设计周期,提高开发效率。
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  相似匹配句对
     Design
     设计
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     To design the G.
     在设计G.
短句来源
     TIMING OPTIMAL DESIGN IN RTL CIRCUIT
     RTL电路的时序优化设计
短句来源
     Optimization of Architecture for Viterbi Decoder on RTL Design Stage
     Viterbi解码器RTL设计优化
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  rtl design
A methodology aimed at better integration of functional verification and RTL design
      
RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage
      
The purpose of this paper is to present a RTL design and test methodology allowing the identification of design errors and difficult to verify functional parts.
      
An RTL design of the continuum block will be developed.
      
Consequently, the performance of the RTL design may actually degrade.
      
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When more and more mobile equipments are needed and the frequency of chips is increased, the power of chips are more and more considered by designers. The evaluation of the total performance of chips is changed from areas and speed of chips to areas ,timing ,testability and power of chips ,and power will play more and more important role in the total performance.In this paper, we mainly discuss how to implement low power designs in RTL designs.

随着移动设备需求量的不断增大和芯片工作速度的不断提高 ,芯片的功耗已经成为电路设计者必须考虑的问题 ,对于芯片整体性能的评估已经由原来的面积和速度的权衡变成面积、时序、可测性和功耗的综合考虑 ,并且功耗所占的权重会越来越大 .本文主要讲述在 RTL 设计中如何实现低功耗设计 .

In VLSI design, gate level fault simulation is often too slow to meet the demand of time-to-market. Thus the register transfer level(RTL) fault simulation has become a hot topic recently. Some RTL fault simulation methods have been proposed, but to get the total system fault coverage, the calculation of fault numbers or weighted coefficients need to synthesize RTL design into netlist. Based on signal sizes and operators, a method of RTL fault number prediction is proposed, and then a pure RTL fault coverage...

In VLSI design, gate level fault simulation is often too slow to meet the demand of time-to-market. Thus the register transfer level(RTL) fault simulation has become a hot topic recently. Some RTL fault simulation methods have been proposed, but to get the total system fault coverage, the calculation of fault numbers or weighted coefficients need to synthesize RTL design into netlist. Based on signal sizes and operators, a method of RTL fault number prediction is proposed, and then a pure RTL fault coverage calculation method is developed in the paper. The experimental result proves the efficiency of the methods.

在超大规模集成电路设计过程中 ,门级故障仿真通常因仿真速度太慢而不能满足市场需求 ,因此近年来寄存器传输级 (RTL)故障仿真成了一个研究热点 已有的RTL的故障模型和故障仿真方法在计算系统的故障覆盖率时 ,对故障数目或者加权系数的计算需要将RTL设计综合到门级 文中在信号位宽和运算符类型的基础上 ,提出了一种在RTL预测故障数的手段 ,并由此得到完全RTL的故障覆盖率计算方法 实验结果证明了该方法的有效性

The original partition strategy often causes less optimization result when used to verify the functions of SOC with multi-FPGA’s.Even the cost of design is so high that designers have to redesign the system.In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.The result of partition demonstrates that the method could significantly improve the efficiency of functional verification and the...

The original partition strategy often causes less optimization result when used to verify the functions of SOC with multi-FPGA’s.Even the cost of design is so high that designers have to redesign the system.In this paper, on the basis of static timing analysis, a new method is employed to enhance the efficiency of FPGA partition by extracting the information of critical path-delay.The result of partition demonstrates that the method could significantly improve the efficiency of functional verification and the utilization ratio of CLB’s and I/O.Finally, the advantage of co-verification dealing with the interrelation between signal integrity and RTL design is discussed.

 利用多片FPGA对SOC系统进行功能验证时,原始的系统分割策略常常导致欠优化的结果,有时甚至会付出重新设计的高昂代价。文章在静态时序分析的基础上,提出了一种利用关键路径时延信息提高FPGA分割效率的方法。分割结果表明,该方法能显著改善功能验证效率,明显提高逻辑控制块和I/O的利用率。文中同时讨论了该协同验证策略在处理信号完整性与RTL设计脱节时所具有的优势。

 
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