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电路时延
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  circuit delay
     Thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages.
     它们将若干复杂指令操作均匀分配在几个流水节拍内完成,实现了任意窗口寻址等复杂指令操作,将整个处理器的数据通路与控制通路分离,减小了电路时延,从而满足了RISC/DSP不同指令功能和系统时钟频率的要求,构成了统一的、紧密联系的、协调的MD32系统结构。
短句来源
     In order to obtain more accurate circuit delay,the notion of the global false path is applied to a previous timing analysis of circuits and a new timing characterization method was presented for improving the accuracy of timing models.
     为了得到确定精确的电路时延,将全局伪路径的观念引入到电路时钟特性分析中,提出了一种改进电路模块时钟周期准确性的方法.
短句来源
  “电路时延”译为未确定词的双语例句
     The accelerator is implemented with multiple levels of bit manipulator instead of MUX,it reduces the time complexity of the accelerator from O(N) to O(log 2 N).
     该方法通过使用分层位操作电路取代分层MUX选择电路实现位操作加速来减少电路时延,使得位操作加速器的时间复杂度从O(N)降到了O(log 2 N)。
短句来源
     To realize the hamming distance generator on FPGA, several schemes of the adder that is the key component of the generator are studied. Their simulation waveform and the statistic result of the processing delay and the FPGA resources occupied are also given. Then a new adder realization scheme is given, which can greatly shorten the delay of the circuit and save the FPGA resources.
     汉明距离是用来衡量 2个二进制码字之间的相似程度的 ,本文主要针对用FPGA实现的汉明距离发生器 ,详细研究了其关键部件累加器的几种实现方案 ,给出了波形仿真结果和时延及占用FPGA资源的统计结果 ,提出了一种能大大缩短电路时延、提高运算速度并节省资源的实现方案 ,最终用FPGA实现并应用于一种卫星通信的帧同步系统中
短句来源
     Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
     工业测试实例实验表明 ,该算法能够有效地优化电路时延 ,满足时延约束
短句来源
     It pays much attention to critical path topologies and transforms the optimization for path delay into cell location optimization. A tracelist determining the order of cell optimization is built and an efficient approach is used to find the target locations of cells that are directly connected to a path.
     该算法基于对电路时延图的拓扑结构分析,将优化关键路径时延的问题转换成优化关键路径上单元位置的问题,通过建立优化位置单元的队列链表,采用一种新的等分节点法有效地寻找路径上单元的目标位置,从而优化路径上的线网长度,最终达到优化最长路径时延的目的.
短句来源
     The principles of measuring the distortion and delay are discussed. The design based on the DSP and FPGA are alsogiven.
     详细阐述了电路时延、失真度等关键参数的测量原理,和基于高性能数字信号处理器DSP与可编程逻辑门阵列FPGA的软、硬件设计过程,针对其中的难点问题,提出了改进与优化措施,为其它信号发生器的设计提供了参考。
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  相似匹配句对
     Basic Direct Current Circuits
     直流电路
短句来源
     Communications ICs
     通信电路
短句来源
     Time Delay Estimation and Data Analysis of Parallel Interconnect Lines in High Speed Circuits
     高速电路平行互连线时延估算与数值分析
短句来源
     Piecewise Delay Modeling of MOS VLSI Digital Circuits
     MOS VLSI数字电路分区间时延建模方法
短句来源
     Delay Characteristics for the Asynchronous Tranfer Mode
     异步传送模式的时延特性
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  circuit delay
Such models, including the commonly-used "unit-delay" model, are shown to significantly misrepresent circuit delay behaviour, particularly with respect to critical paths and long false paths.
      
In lowVDD, however, circuit delay increases and chip performance degrades.
      
A path tracing algorithm for asymptotic waveform evaluation of lumped RLC circuit delay models.
      
As expected, the NPG has a larger circuit delay variation range than the NAND4.
      
At larger inputs, the last stages in the cascade will slew-rate limit and prolong the circuit delay.
      
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The time-delay spread for a HF ionospheric channel is a very important factor affecting the bit-error-rate of a data HF communication system. It is usually obtained using sweep-frequency pulse sounding technique. The measured data show that for a given circuit, the time-delay spread for a specific frequency approximately follows a normal distribution. The standard deviation is linear with the mean value of the time-delay spread. The relationship of the mean value with the frequency can be represented as a empirical...

The time-delay spread for a HF ionospheric channel is a very important factor affecting the bit-error-rate of a data HF communication system. It is usually obtained using sweep-frequency pulse sounding technique. The measured data show that for a given circuit, the time-delay spread for a specific frequency approximately follows a normal distribution. The standard deviation is linear with the mean value of the time-delay spread. The relationship of the mean value with the frequency can be represented as a empirical parabolic representation.

在分析大量观测数据的基础上,本文给出了高频电离层信道时延散布的某些统计特性。根据这些特性,本文提出了一个估算给定电路时延散布的预测方法。

In this paper a new algorithm for technology mapping is presented. The problem is to map minimized logic functions in factored form into a library of predesigned CMOS cells. A tree representation with some attributes and an efficient heuristic algorithm lead to good results implemented in TTMAP. The results obtained are better than with MISII.

用多级逻辑实现控制器的逻辑综合,工艺映射是其中的一个重要步骤。本文叙述的工艺映射算法TTMAP,是在映射过程中考虑了电路的时延与芯片面积等性能因素,在多级逻辑综合中将因子化的逻辑函数映射为CMOS的串并赶电路单元,产生可布图的网表文件。本算法在比利时HMEC研究中心开发,为多级逻辑综合系统MLL中的一个模块。经实例运行,与美国加州大学柏克莱分校的MISⅡ软件相比,本算法的结果较优。

The application of multiple-valued logic to model capacitors in MOS circuits is discussed in this paper.Based on this model,new methods for MOS dynamic circuit analysis,delay analysis and charge sharing analysis are proposed.

本文应用多值开关级代数为MOS电路中的电容建立模型,并提出了应用多值开关级代数分析MOS动态电路、时延及电荷共享的方法。

 
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