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   总线电压 的翻译结果: 查询用时:0.509秒
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总线电压
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  bus voltage
     At input AC voltage 180~255V and output 48V/100W,the DC bus voltage can be limited within 400V.The measured input current harmonics satisfy the IEC 1000 3 2 Class D requirements,efficiency is about 85% and PF is about 0.91.
     在交流输入电压为 1 80~ 2 55V、输出为 48V/1 0 0W情况下 ,直流总线电压被控制在 40 0V以下。 输入电流谐波满足IEC 1 0 0 0 3 2ClassD要求 ,效率为 85% ,功率因数达 0 .91。
短句来源
     This paper introduces a single stage power factor correction AC/DC converters with DC bus voltage feedback. By adding transformer windings,DC bus voltages at high line input and light load are suppressed.
     详细分析了一种单级功率因数校正AC/DC变换器 ,通过增加变压器绕组反馈直流总线电压 ,以抑制输入高压、轻载情况下过高的直流总线电压
短句来源
     On the basis of the new single-stage PFC converter, the paper adds an additional transformer winding, forming the bus voltage feedback to further reduce the voltage across the energy-storage capacitor but to reduce the power factor.
     论文在新型单级PFC变换器的基础上,增加一个变换器附加绕组,引入总线电压反馈,进一步降低储能电容电压,但变换器功率因数随之降低。
短句来源
     The V _ bus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in which a long channel length NMOS is used to substitute a large biasing resistance to save chip area.
     通过采用集成在 SPIC内部的延迟电路 ,使有 APFC电路的总线电压由 6 0 0 V下降为 40 0 V.在电路中 ,采用长沟道的 NMOS管来代替大电阻以节省版图面积 .
短句来源
     Diverting-current and feedback bus voltage are measured during experiments on series Li-ion battery packs equalization charging.
     在锂离子电池组的均衡充电试验过程中,测量了模块的分离电流和反馈总线电压.
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  “总线电压”译为未确定词的双语例句
     The paper presents the theoretical analysis of input current distortion, deducing the relation between inductance and energy-storage capacitor voltage and designing the main circuit and close loop parameters.
     论文对引入总线电压反馈后的输入电流畸变进行了理论分析,推导出Boost电感和储能电容电压的关系,设计了主电路参数和闭环参数,并给出仿真和实验波形,验证设计的合理性。
短句来源
  相似匹配句对
     ⑦total work load.
     ⑦工作量。
短句来源
     IRONMAKING SUM CONTENTS IN BRIEF
     炼铁目次
短句来源
     Diverting-current and feedback bus voltage are measured during experiments on series Li-ion battery packs equalization charging.
     在锂离子电池组的均衡充电试验过程中,测量了模块的分离电流和反馈线电压.
短句来源
     On-Line Voltage Control for Power Systems
     电力系统在线电压控制
短句来源
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  bus voltage
The detector's voltage can turn off the switch of the APFC (Active Power Factor Correction) circuit and the bus voltage would fall from 600VDC to 300VDC, so the SPIC and power devices can be protected.
      
The triangular carrier waveform used in soft-switching PWM inverter will cause difficulties in controlling resonance-trigger time, higher loss in the resonant circuit, and less utilization of the DC bus voltage.
      
It is a quadratic function of bus voltage angles and can easily be calculated from real power flows or DC load flow.
      
Advantageous SRM power converter topologies have been proposed over the years, however, some of them were utilizing a large number of discrete power components, while the others were leading to a poor utilization of the DC-bus voltage.
      
In this article, a novel SRM drive is proposed, entirely based on standard industrial inverter modules, fully utilizing bus voltage.
      
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This paper introduces a single stage power factor correction AC/DC converters with DC bus voltage feedback.By adding transformer windings,DC bus voltages at high line input and light load are suppressed.At input AC voltage 180~255V and output 48V/100W,the DC bus voltage can be limited within 400V.The measured input current harmonics satisfy the IEC 1000 3 2 Class D requirements,efficiency is about 85% and PF is about 0.91.

详细分析了一种单级功率因数校正AC/DC变换器 ,通过增加变压器绕组反馈直流总线电压 ,以抑制输入高压、轻载情况下过高的直流总线电压。在交流输入电压为 1 80~ 2 55V、输出为 48V/1 0 0W情况下 ,直流总线电压被控制在 40 0V以下。输入电流谐波满足IEC 1 0 0 0 3 2ClassD要求 ,效率为 85% ,功率因数达 0 .91。

A novel SPIC(smart power IC) with a simple APFC(active power factor correction) circuit on one chip is proposed.The V _ bus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in which a long channel length NMOS is used to substitute a large biasing resistance to save chip area.The lower V _ bus results in a smaller R _ on (on-resistance) of power switcher,which reduces the power loss of the power devices,improves the efficiency of the circuit,and reduces the cost of...

A novel SPIC(smart power IC) with a simple APFC(active power factor correction) circuit on one chip is proposed.The V _ bus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in which a long channel length NMOS is used to substitute a large biasing resistance to save chip area.The lower V _ bus results in a smaller R _ on (on-resistance) of power switcher,which reduces the power loss of the power devices,improves the efficiency of the circuit,and reduces the cost of circuits.An integrated high voltage over voltage protect circuit is also designed in the circuits.Theory and simulations both prove the correctness and availability of the design.

提出了一种新型的具有简易 APFC的单片 SPIC电路 .通过采用集成在 SPIC内部的延迟电路 ,使有 APFC电路的总线电压由 6 0 0 V下降为 40 0 V.在电路中 ,采用长沟道的 NMOS管来代替大电阻以节省版图面积 .在保证所需的功率因数的情况下 ,总线电压的下降可以直接导致功率开关器件的比导通电阻下降 ,减小功率器件的损耗 ,提高电路的效率 .同时 ,总线电压下降 ,也使电路成本降低 .此外 ,还同时设计了相应的高压过压保护电路 .理论分析与模拟结果都证明该设计是正确的和有效的 .

Design of an I~2C Specific bidirectional open-drain I/O buffer is proposed .Some key electronic characteristics which are defined in the specification are solved in this design such as LOW/HIGH level input voltage, output fall time. This design also employ some structures for mix-voltage applications; including a level converter which is interconnect with (1.8 V) core module, a voltage protector which supply (5 V) compatible usage. The layout of the circuit is briefly illustrated .The circuit is designed and...

Design of an I~2C Specific bidirectional open-drain I/O buffer is proposed .Some key electronic characteristics which are defined in the specification are solved in this design such as LOW/HIGH level input voltage, output fall time. This design also employ some structures for mix-voltage applications; including a level converter which is interconnect with (1.8 V) core module, a voltage protector which supply (5 V) compatible usage. The layout of the circuit is briefly illustrated .The circuit is designed and simulated in (0.18 μm) duel voltage (1.8 V/3.3 V) CMOS technology. The circuit complies with I~2C fast-mode I/O stages electrical Specification.

符合标准的电气参数实现是设计的主要问题,详细阐述了一些关键参数的实现方式,如输入高低电平、输出下降时间。为适应多电压的工作环境,电路采用了一些特殊结构如采用电平转换单元和内部低电压电路互联、采用电压保护结构使电路同时支持3.3 V和5 V 总线电压。该电电路采用常见的双电压(1.8 V/3.3 V)0.18μm工艺实现。仿真结果表明完全符合飞利浦公司的快速型 I2C总线(FAST-MODE)的电气标准。

 
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