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rtl模拟
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  “rtl模拟”译为未确定词的双语例句
     Research On RT-Level Automatic functional vectors generation
     RTL模拟矢量自动生成技术研究
     This paper presents and implements an automatic functional vectors generation framework - HRV for RTL designs. HRV integrated program slicing based design extractor, VCD file based cgverage analyzer, path-based and assertion-based automatic simulation vectors generator, which are all developed by ourselves.
     本文设计并实现了一个RTL模拟矢量自动生成原型系统HRV,它集成了自主开发的基于程序切片技术的设计抽取器、基于VCD文件的代码覆盖率分析器、以及基于路径和基于断言的模拟矢量自动生成方法。
  相似匹配句对
     RTL Symbolic Simulation System
     RTL级符号模拟系统
短句来源
     Research On RT-Level Automatic functional vectors generation
     RTL模拟矢量自动生成技术研究
     Statistical Simulation
     统计模拟
短句来源
     Simulation of distillation process
     精馏过程的模拟
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  rtl simulation
After the validation of the virtual architecture and the generation of RTL architecture as shown in Figure 1, we generated an RTL simulation model.
      
A program was also written to compare the Scanout data with RTL simulation to aid in interpreting the data.
      
Later, RTL simulation is performed to verify the hypothesis made based on the collected data and to identify the failing node.
      
Not only the FPGA board verifies the same behavior in RTL simulation, but also directly performs recognition experiments via a microphone.
      
RTL simulation was used to validate the remaining assertions based on the given set of test cases.
      
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>=is the key to improve the quality of simulation and shorten verification cycle. This paper presents and implements an automatic functional vectors generation framework - HRV for RTL designs. HRV integrated program slicing based design extractor, VCD file based cgverage analyzer, path-based and assertion-based automatic simulation vectors generator, which are all developed by ourselves. Experimental results show that HRV improved the efficiency of simulation verification, accelerated the errors detecting and...

>=is the key to improve the quality of simulation and shorten verification cycle. This paper presents and implements an automatic functional vectors generation framework - HRV for RTL designs. HRV integrated program slicing based design extractor, VCD file based cgverage analyzer, path-based and assertion-based automatic simulation vectors generator, which are all developed by ourselves. Experimental results show that HRV improved the efficiency of simulation verification, accelerated the errors detecting and locating for RTL HDL descriptions.

模拟矢量自动生成是提高VLSI验证质量、缩短验证周期的关键。本文设计并实现了一个RTL模拟矢量自动生成原型系统HRV,它集成了自主开发的基于程序切片技术的设计抽取器、基于VCD文件的代码覆盖率分析器、以及基于路径和基于断言的模拟矢量自动生成方法。实验结果表明,HRV可有效提高模拟验证效率,加速错误检测和错误定位。

 
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