助手标题  
全文文献 工具书 数字 学术定义 翻译助手 学术趋势 更多
查询帮助
意见反馈
   时钟时延 的翻译结果: 查询用时:0.02秒
图标索引 在分类学科中查询
所有学科
无线电电子学
更多类别查询

图标索引 历史查询
 

时钟时延
相关语句
  clock delay
     The circuit can be used to remove clock delay. The unconditionally stable fully digital DLL architecture does not accumulate phase error ,and offers advantages in noise sensitivity and lower power consumption.
     该电路用于消除时钟时延 ,全数字的结构使其无条件稳定 ,不会累积相位误差 ,而且具有良好的噪声敏感度、较低的功耗和抖动性能。
短句来源
  相似匹配句对
     Estimation of Clock Skew in Delay Measurement
     时延测量中估算时钟时滞的方法
短句来源
     Clock Synchronization Algorithm for Internet Delay Measurements
     Internet网络时延测量中的时钟同步算法
短句来源
     The clock sings
     时钟的歌唱
短句来源
     Stability of networked control systems with time-delay
     时延网络控制系统的稳定性
短句来源
     Delay Characteristics for the Asynchronous Tranfer Mode
     异步传送模式的时延特性
短句来源
查询“时钟时延”译词为用户自定义的双语例句

    我想查看译文中含有:的双语例句
例句
为了更好的帮助您理解掌握查询词或其译词在地道英语中的实际用法,我们为您准备了出自英文原文的大量英语例句,供您参考。
  clock delay
Compared with the method of buffer insertion after zero skew clock routing, our method improves the maximal clock delay by at least 48%.
      
Compared with legitimate skew clock routing algorithm with no buffer, this algorithm further decreases the total wire length and gets reductions from 42 to 82% in maximal clock delay.
      
Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.
      
A zero-skew clock tree optimization algorithm for clock delay and power optimization is proposed.
      
An extra clock delay is required by the comparator and the D-type ipop.
      
更多          


This paper presents a delay locked loop (DLL) circuit that can be implemented with fully digital circuits. It is different from phase locked loops(PLL) and delay locked loop based on voltage controlled delay line(VCDL). The circuit can be used to remove clock delay. The unconditionally stable fully digital DLL architecture does not accumulate phase error ,and offers advantages in noise sensitivity and lower power consumption. The architecture and performance of the circuit have advantages in delay compensation...

This paper presents a delay locked loop (DLL) circuit that can be implemented with fully digital circuits. It is different from phase locked loops(PLL) and delay locked loop based on voltage controlled delay line(VCDL). The circuit can be used to remove clock delay. The unconditionally stable fully digital DLL architecture does not accumulate phase error ,and offers advantages in noise sensitivity and lower power consumption. The architecture and performance of the circuit have advantages in delay compensation and clock adjustment. It can be completely incorporated on a single silicon chip. The paper analyses the principle and the architecture of the circuit,and suggests an application of the circuit in FPGA.

介绍了一种区别于锁相环 (PLL )和基于压控延迟线 (VCDL )的延时锁定环 (DLL )、全部由纯数字电路实现的 DL L电路。该电路用于消除时钟时延 ,全数字的结构使其无条件稳定 ,不会累积相位误差 ,而且具有良好的噪声敏感度、较低的功耗和抖动性能。使其在时延补偿和时钟调整的应用中具有优势 ,并可全部嵌入单个芯片中。文中分析了全数字 DL L的工作原理及其结构 ,给出了其在现场可编程门阵列 (FPGA)中的应用。

 
图标索引 相关查询

 


 
CNKI小工具
在英文学术搜索中查有关时钟时延的内容
在知识搜索中查有关时钟时延的内容
在数字搜索中查有关时钟时延的内容
在概念知识元中查有关时钟时延的内容
在学术趋势中查有关时钟时延的内容
 
 

CNKI主页设CNKI翻译助手为主页 | 收藏CNKI翻译助手 | 广告服务 | 英文学术搜索
版权图标  2008 CNKI-中国知网
京ICP证040431号 互联网出版许可证 新出网证(京)字008号
北京市公安局海淀分局 备案号:110 1081725
版权图标 2008中国知网(cnki) 中国学术期刊(光盘版)电子杂志社