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   乘法电路 的翻译结果: 查询用时:0.568秒
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乘法电路     
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  multiplication circuit
     Encoder is the foundation of quick multiplication arithmetic. The new encoder method is based on the research that how encoding will impact switching probability of multiplication circuit.
     考虑到编码结果对乘法电路翻转概率的影响,本文提出了一种改进低功耗Booth编码方法,该方法相比传统的Booth编码方法,在适当增加延迟和面积的条件下可以有效降低功耗。
短句来源
     In This paper, a new byte parallel multiplication component of Galois field for RS encoder in DVB-S front end baseband processor in propsed. The multiplication circuit only involves the polynomial operation which is composed of bit-mul- tiply and hit-add based on the binary system vector of conventional basis, it effective improves the processing speed of the whole system.
     针对DVB-S前端基带处理系统的RS编码提出比特并行的迦罗华域乘法部件,乘法电路中所涉及的仅仅是自然基下二进制向量表示中二进制数的位乘(按位与)和位加(按位异或)的组合所代表的多项式运算,有效的提高了整个系统的处理速度。
短句来源
  multiplying circuit
     A new CMOS four quadrant multiplier based on the MOSFET current-voltage sqa-re law is proposed. The multiplier uses a voltage ratio circuit and a four-transistor cell multiplying circuit which enable its precision multiplying operation.
     本文提出了一种新型CMOS四象限乘法器,它基于MOSFET的电流-电压平方律模型,采用电压比例电路及四管单元乘法电路使乘法器能精确完成乘法运算。
短句来源
  multiplier circuit
     The Multiplier Circuit with the Controlled Resistance of FET
     FET可变电阻乘法电路
短句来源
     Based on the design of the high-speed multiplier circuit, this article ends up realizing the IQ and IDCT of MPEG-2 video decoder with FPGA.
     通过对高速乘法电路算法的研究,本文提出了一种基4 Booth算法的硬件乘法器电路,为了提高硬件乘法器电路的运算速度,本文使用了4-2压缩器和3-2压缩器、华莱士树、以及并行和流水线算法等。
短句来源
  “乘法电路”译为未确定词的双语例句
     An Economical and Practical PWHM Analog Multiplier
     一种经济实用的PWHM式模拟乘法电路
短句来源
     The New Circuits Implementing Decoding of Reed Solomon (RS) Codes
     实现Reed Solomon码译码的新电路——在普通基上用“比特串行乘法电路”实现RS码译码
短句来源
     The detailed implementations of circuit blocks, such as gain, sum, multipliers, VCVS(Voltage Controlled Voltage Source ) and VCCS(Voltage Controlled Current Source ), are discussed.
     本文还给出了模拟VLSI模型部分功能模块的具体电路如增益电路、加法电路、乘法电路、电压控制电压源、电压控制电流源等。
短句来源
     In order to improve the process speed, substitute the shift-and-add circuits for multipliers in datapath.
     每路数据通道采用流水线结构,其中乘法电路由移位相加电路构成以提高运算速度;
短句来源
     Two circuit structures which are the optimized multiplier with full-adder array and the serial-parallel multiplier with pipeline inside are put forward.
     提出了普通阵列乘法电路的改进结构和含流水线的串并乘法电路(SPM)结构。
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      multiplication circuit
    Lastly, a parallel multiplication circuit is proposed as an example to show the effectiveness and the application of this design in terms of functionality and fault-tolerance.
          
      multiplier circuit
    The use of CDBA in fully-integrated multiplier circuit design is attractive, since it simplifies the implementation and reduces the component count while maintaining good performance.
          
    In the development of a monolithic diode-grid frequency multiplier array, the low-loss quasioptical configuration is used for the construction of the multiplier circuit.
          
    A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented.
          
    This design results in a more compact wiring structure and balanced delays resulting in a faster multiplier circuit.
          
    Architecture of the Montgomery modular multiplier circuit length l are given in Table 2.
          
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    A new CMOS four quadrant multiplier based on the MOSFET current-voltage sqa-re law is proposed. The multiplier uses a voltage ratio circuit and a four-transistor cell multiplying circuit which enable its precision multiplying operation. The simple circuit structure, high precision operation and four quadrant multiplying capability features make the multiplier widely applicable to CMOS communication ICs, signal processing equipments and electronic computing systems. A detailed analysis on the design and the circuit...

    A new CMOS four quadrant multiplier based on the MOSFET current-voltage sqa-re law is proposed. The multiplier uses a voltage ratio circuit and a four-transistor cell multiplying circuit which enable its precision multiplying operation. The simple circuit structure, high precision operation and four quadrant multiplying capability features make the multiplier widely applicable to CMOS communication ICs, signal processing equipments and electronic computing systems. A detailed analysis on the design and the circuit structure is given and the simulated results using HSPICE-II is presented.

    本文提出了一种新型CMOS四象限乘法器,它基于MOSFET的电流-电压平方律模型,采用电压比例电路及四管单元乘法电路使乘法器能精确完成乘法运算。该乘法器的电路结构简单、精确度高及实现四象限相乘的特点,使之在CMOS通信集成电路,信号处理及运算电子系统中有广阔的应用前景。文中对电路的结构进行了详细分析和设计,并给出了HSPICE-Ⅱ模拟结果。

    This paper reviewes principle of power de-tection in the Steel-Smelting control System The multiplication circuits and interface circuits are analscd. The measures for incrcasing accuracy of detection, increasing speed of response and ability of anti-disturbance etc, are presented. Then the link of detection is analysed with practical measuring data.

    本文论述了炼钢控制系统的功率检测原理,分析了它的乘法电路和接口电路,并在提高检测精度、提高响应速度及抗干扰等方面提出了措施,最后结合具体测试数据进行了分析。

    We present a multiplier circuit,based on the principle of FET resistance control.The theory of this cricuit is discussed and the quantitative relation is derived.Furthermore,the circuit error is analysed and practical example is given .

    介绍了一种基于FET漏源极间电阻可控的原理所构成的乘法电路,论述了电路原理,推导了量值关系,分析了电路误差,最后给出了实用的电路例子.

     
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