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加法阵列
相关语句
  adder array
     The timing requirements for PE structure and the adder array for adder tree structure to optimize performance of design are studied and used.
     研究了并利用PE(处理单元)结构时序约束和加法树结构的加法阵列优化设计性能。
短句来源
  “加法阵列”译为未确定词的双语例句
     The present paper primary mission is reorganize circuit and circuit simulation after the parallel multiplier original domain electric circuit, The parallel multiplication accumulator (MAC) has three main parts: The partial product producer (Booth Encode unit), the addition array unit (Mult unit) and carries transmits adder(ACC unit).
     本论文的主要任务是在并行乘法器的原版图电路提取之后,对电路进行分块整理,原理仿真。 并行乘法累加器(MAC)有三个主要部分:部分积产生器(Booth Encode unit),加法阵列模块(Mult unit)和进位传输加法器(ACC unit)。
短句来源
     The addition array module uses the CSA array accumulator, the transmission delay which with Wallace the Tree structure, reduced the massive partial products adds together when produces, optimized the partial product accumulation process, enhanced the whole operating speed;
     加法阵列模块采用CSA阵列加法器,和Wallace Tree结构,减少了大量部分积相加时所产生的传输延迟,优化了部分积的累加过程,提高了整体运算速度;
短句来源
     The FIR architecture is based on a pipelined multiply add accumulator(MAC)which employs carry save array.
     该结构采用基于流水线型的乘加器和进位保留的加法阵列
短句来源
  相似匹配句对
     The Mierolen Array
     微透镜阵列
短句来源
     A CALORIMETER WITH ARRAY DETECTORS
     量热器阵列探测器
短句来源
     The FIR architecture is based on a pipelined multiply add accumulator(MAC)which employs carry save array.
     该结构采用基于流水线型的乘加器和进位保留的加法阵列
短句来源
     Weak Additive Category
     弱加法范畴
短句来源
     Sony Ericsson's Addition Future
     索爱的“加法未来”
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  adder array
The delays of the bits processed by the ith column of the adder array, are organized into a sequence Dk i for modulo m operation.
      
The delays of the bits processed by the th column of the adder array, are organized into two sequences and for modulo and operation, respectively.
      


A digital FIR filter architecture implemented in FPGA is described.The FIR architecture is based on a pipelined multiply add accumulator(MAC)which employs carry save array.To save the delay time and hardware resources,multiplier uses the partial products generated by modified Booth algorithm.The FIR architecture is written in VHDL,and is synthesized into FPGA.The synthesis result shows that the proposed FIR architecture can run at 50 MHz clock...

A digital FIR filter architecture implemented in FPGA is described.The FIR architecture is based on a pipelined multiply add accumulator(MAC)which employs carry save array.To save the delay time and hardware resources,multiplier uses the partial products generated by modified Booth algorithm.The FIR architecture is written in VHDL,and is synthesized into FPGA.The synthesis result shows that the proposed FIR architecture can run at 50 MHz clock rate in FPGA XC4025e 2.

讨论了一种在FPGA中可实现的FIR滤波器结构。该结构采用基于流水线型的乘加器和进位保留的加法阵列。为减少硬件消耗,乘法器使用的部分积由修改的Booth算法产生。FIR滤波器用VHDL进行描述,并综合到FPGA中。从综合结果来看,提出的FIR结构可以在XC4025e-2中以50MHz的时钟频率高速运行。

The binary complement square function is a special multiplier often used in digital circuits and digital ASICs. This paper presents a novel fast algorithm, whose partial products come from the components of the much lower rank multiplier and square. This algorithm shortens the addition delay greatly with only five partial products, and decreases the resource to a certain degree.

针对二进制补码平方运算的特点 ,提出了一种快速实现算法 ,即利用专用集成电路设计中的标准单元库中低位乘法 (平方 )构件或通过其他算法实现的模块 ,并经部分积重组而形成更少的部分积 ,行数仅 5行 ,与平方位宽无关 ,极大地缩短了加法阵列的计算时间 ,同时在一定程度上减少了系统所用资源 .

In this paper, a 17×17+40 multiply-and-accumulator (MAC) unit with high performance is presented. By merging the MAC operation to regular multiply operation the MAC performance is enhanced. To shorten the critical path in the multiplier, we use the Modified Booth encoder technology and a new method which adds special Partial-Product in adder-array to avoid the sign-bit extension and the add operation in the Partial-Product generation unit. Finally the design is coded with Verilog HDL and synthesized based on...

In this paper, a 17×17+40 multiply-and-accumulator (MAC) unit with high performance is presented. By merging the MAC operation to regular multiply operation the MAC performance is enhanced. To shorten the critical path in the multiplier, we use the Modified Booth encoder technology and a new method which adds special Partial-Product in adder-array to avoid the sign-bit extension and the add operation in the Partial-Product generation unit. Finally the design is coded with Verilog HDL and synthesized based on the ASIC technology lib; the resource and delay analysis have also been done.

本文介绍一个高性能的 17位乘 17位加 4 0位的乘加单元 (MAC)的设计 ,通过将被加数作为乘法器的一个部分积参与到部分积加法阵列中来完成整个乘加运算 ,大幅度地提高了MAC单元的性能 ,在乘法器的设计中采用了改进的Booth编码技术 ,并且通过添加特定的部分积来避免部分积的符号位扩展和部分积产生单元中的加法操作 ,缩短了乘法器中关键路径的长度 ,最后利用HDL对设计进行描述 ,结合ASIC工艺库进行了综合以及资源和时延分析

 
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