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二级cache
相关语句
  level two cache
     The Design and Study of Level Two Cache Controller on High Performance DSP Chip
     高性能DSP片内二级Cache控制器设计研究
短句来源
  “二级cache”译为未确定词的双语例句
     In our self-determined design of YHFT_D1, the Second Level Cache Controller (L2), which is programmable, has been adopted.
     在我们自主研制的YHFT_D1中采用片内两级Cache层次,且二级Cache控制器(简称L2)是可编程控制的。
短句来源
     It introduces the architecture of Intel P4 Microprocessor memory, includes L1 data Cache, L2 Cache, Trace Cache;
     文中介绍了P4处理器内存的体系结构,它包括一级数据Cache、二级Cache、TraceCache;
短句来源
     4. Completed the design of the "Longtium D2" L2 cache, including the architecture design, hardware support, interconnection mechanism and the state machine of main controller etc.
     4.完成了“龙腾D2”双核处理器中二级Cache的设计,包括整体结构的设计、硬件支持、互联机制、主控状态机的设计等。
短句来源
     2. Based on the successful implementation of "Longtium R2", this paper researched the CMP architecture, analyzed the cache hierarchy and interconnection of the dual core processor and proposed the cooperative cache, which is suitable for "Longtium D2" microprocessor.
     2.在完成“龙腾R2”的研究基础上,对单片多处理器体系结构进行研究,分析了双核处理器Cache层次以及互联结构,并提出适用于“龙腾D2”双核处理器体系结构的协同式二级Cache的设计方案。
短句来源
     In order to reduce the miss delay of L2 cache of YHFT-Dx, we further optimized the interface protocol besides adding a direct path from L2 to EMIF. We also set write buffer and adopted 'Requested Word First' technique between data cache and L2, between EMIF and L2, all of which improve the performance of cache system.
     为了减小YHFT-Dx二级Cache的失效延迟,在已增设的1,2与外部存储器接口(EMIF)直接通路基础上进一步优化了接口协议,并通过在EMIF与L2之间、一级数据Cache与L2之间设置写回缓冲和优先供给请求字,大大提高了Cache系统的性能。
短句来源
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  相似匹配句对
     The Design and Study of Level Two Cache Controller on High Performance DSP Chip
     高性能DSP片内二级Cache控制器设计研究
短句来源
     The Leakage Power Optimization in On-Chip L2 Caches
     片内二级Cache的静态功耗优化技术研究
短句来源
     Cache Profiling
     Cache Profiling技术
短句来源
     BORING SECONDARY SPECTRAL LINE
     烦人的二级光谱线
短句来源
     RNA Secondary Structure
     RNA的二级结构
短句来源
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  secondary cache
A victim write is issued by a CPU module when a block is evicted from the secondary cache.
      
During this period he led the logic design of secondary cache controllers for the 50MHz i486, i860XP, and the 66Mhz Pentium.
      
For CPU modules, the RAM lookup does not reduce performance, since the access is done in parallel with the access of the module's secondary cache.
      
If the block is in the on-chip cache, the secondary cache accepts the update and invalidates the block in the on-chip cache.
      
If the block is not in the on-chip cache, the secondary cache block is invalidated.
      
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  level two cache
There is a central atomic bus connecting the CPU nodes together with a unified level two cache.
      


Generally the processor has on-chip cache,which is composed of fixed-size top level cache(L1Cache)and second level cache(L2Cache).This paper introduces a dynamically configurable cache structure implemented in the embedded processor design.The idea of dynamically reconfigurable cache originally appeared in a paper about memory-hierarchy,which is written by scholar of University of Rochester 1 .And they aim at high performance superscalar general-purpose processor.During the process we design our embedded...

Generally the processor has on-chip cache,which is composed of fixed-size top level cache(L1Cache)and second level cache(L2Cache).This paper introduces a dynamically configurable cache structure implemented in the embedded processor design.The idea of dynamically reconfigurable cache originally appeared in a paper about memory-hierarchy,which is written by scholar of University of Rochester 1 .And they aim at high performance superscalar general-purpose processor.During the process we design our embedded processor,we inherit this idea in a creative way.By adding a few hardware and by support of the compiler,the size of L1Cache and L2Cache can be dynamically configured according to application while the total size is fixed in the embedded processor.Dynamically configuration can not only raise the hit rate but also reduce the power dissipation efficiently.

一般的处理器芯片都有片上高速缓存Cache,它一般是由固定大小的一级Cache(L1)和二级Cache(L2)构成,文章介绍了一种在嵌入式处理器设计中实现的动态可重构Cache。动态可重构Cache的思想最早是罗彻斯特大学(UniversityofRochester)的学者在他们的一篇关于存储层次的论文1中提出的,当时主要是针对高性能的超标量通用处理器。在此嵌入式处理器设计过程中,笔者创造性地继承了这一思想。通过增加少量硬件以及编译器的配合,在嵌入式处理器中L1Cache和L2Cache总体大小不变的情况下,L1Cache和L2Cache的大小可以根据具体的应用程序动态配置。通过对高速缓存的动态配置,不仅可以有效地提高Cache的命中率,还能够有效降低处理器的功耗。

The efficiency of microprocessor memory is very important to its holistic capability.It introduces the architecture of Intel P4 Microprocessor memory, includes L1 data Cache, L2 Cache, Trace Cache; the function of these portions and the prefetch mechanism which can advance the efficiency by increasing the hit rate and reducing the memory access time. To reduce the access time which can increase the holistic capability of microprocessor, P4 microprocessor adopts these ways: hiberarchy-design, bulky L2 Cache and...

The efficiency of microprocessor memory is very important to its holistic capability.It introduces the architecture of Intel P4 Microprocessor memory, includes L1 data Cache, L2 Cache, Trace Cache; the function of these portions and the prefetch mechanism which can advance the efficiency by increasing the hit rate and reducing the memory access time. To reduce the access time which can increase the holistic capability of microprocessor, P4 microprocessor adopts these ways: hiberarchy-design, bulky L2 Cache and applying prefetcher which can increase the hit rate of cache and reduce the cost of hit failed.

处理器存储系统的效率对其整体性能有着十分重要的作用。文中介绍了P4处理器内存的体系结构,它包括一级数据Cache、二级Cache、TraceCache;各部分完成的功能以及为提高命中率和降低存取时间,从而提高效率而采取的预取处理机制;P4处理器主要采取具有层次结构的内存设计、大容量的二级Cache和在跟踪Cache中采用预取处理机制的方法来提高Cache的命中率和降低未命中的代价来缩短处理器的访问时间,最终达到提高处理器整体性能的目的。

Designsed a new cache system on RAID. This system has the following innovations: (1)Adopting private and dynamic allocation strategy in Deploying cache, and deciding the prime proportion of the private and the public through constructing allocating model.(2)Constructing two-level read cache structure. In this structure, level 1 read cache exploits temporal locality, and level 2 read cache exploits spatial locality.(3)Presenting timing-move and replacing according to a given threshold strategy. This strategy...

Designsed a new cache system on RAID. This system has the following innovations: (1)Adopting private and dynamic allocation strategy in Deploying cache, and deciding the prime proportion of the private and the public through constructing allocating model.(2)Constructing two-level read cache structure. In this structure, level 1 read cache exploits temporal locality, and level 2 read cache exploits spatial locality.(3)Presenting timing-move and replacing according to a given threshold strategy. This strategy is moving the small data blocks which are accessed lately in level 2 caches node to level 1 cache, and replacing the level 2 caches node when small data blocks moved exceeds a given threshold. The paper still proves that timing-move strategy exploits temporal locality effectively and improve the cache system performance through simulation test.

设计了一个新的基于 RAID的 Cache系统 ,本系统有如下创新之处 :(1)在全局配置 Cache时 ,采取了预留与动态分配相结合的策略 ,并建立了分配模型 ,从理论上确定了预留与动态分配的最佳比例 .(2 )建立了二级读 Cache结构 ,其中 :一级读 Cache实现时间的局部性 ;二级读 Cache实现空间的局部性 .(3)提出了定时搬移并按阈值淘汰的策略 ,即定时把二级 Cache的节点中最近访问过的数据小块搬移到一级 Cache,当搬移的数据小块超过一个阈值时 ,淘汰二级 Cache的相应节点 .通过仿真测试证明了定时搬移策略较好地实现了时间的局部性 ,提高了 Cache系统的性能

 
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