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二进制转换
相关语句
  binary conversion
    Hide List Method for 0-1 Programming Based on Binary Conversion
    基于二进制转换的0-1规划隐枚举法
短句来源
  binary conversion
    Hide List Method for 0-1 Programming Based on Binary Conversion
    基于二进制转换的0-1规划隐枚举法
短句来源
  “二进制转换”译为未确定词的双语例句
    Frequency Synthesis Theory for Binary to Decimal Conversion
    二进制转换到十进制的频率合成理论
短句来源
    The principle of Decimal-Binary was applied in inversed order algorithm of DIT-FFT sequence.
    DIT-FFT序列的倒序算法采用了十进制与二进制转换原理规划。
短句来源
    The Way of Decimal Translating into Binary
    十进制与二进制转换算法的研究
短句来源
    A frequency synthesis aeries of binary to decimal conversion and its corresponding block diagram are given.
    本文给出一个二进制转换到十进制的频率综合级数,并给出与其相对应的方框图
短句来源
    Aiming at the method of binary system conversion in data mining,this paper defines binary system sequences set and its related concepts.
    针对在数据挖掘中采用二进制转换的方法,定义了二进制序列集的相关概念并为此提供依据。
短句来源
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  binary conversion
Furthermore, the impact of the binary-to-residue and residue-to-binary conversion on the performance of the ECPM is investigated.
      
Furthermore, the impact of the binary-to-residue and residue-to-binary conversion was investigated.
      
In such a case, the AHSD-to-binary conversion overhead can be amortized over a long sequence of CF additions.
      
This CO2 reduction assumes using binary conversion sys tems with near-zero carbon emissions.
      
The insertion method consists in carrying out a binary conversion then we divide the image into 8 plans of bits.
      


A frequency synthesis aeries of binary to decimal conversion and its corresponding block diagram are given.

本文给出一个二进制转换到十进制的频率综合级数,并给出与其相对应的方框图

In point of the ordinary hide list method, this paper proposes a method that can list all possible solutions efficiently and quickly based on binary conversion, including the rule of arranging all solutions to hence optimizing process. Also an example is given.

本文针对常规隐枚举法 ,提出了一种基于二进制转换的快速有效枚举出所有可能解的方法 ,包括旨在加速优化过程的所有可能解的排列规则 ,并给出了一个算例。

Although the serial implementation of division and square root converges slowly in the floating point unit, the design simplicity, layout regularity and low layout area make this method popular in embedded application. Based on the development of the embedded coprocessor LSC87, the radix 4 SRT algorithm of the implementation for the combination of division and square root is discussed in this paper. The validity of the uncertain region according to the SRT selection constant is verified and the on the fly...

Although the serial implementation of division and square root converges slowly in the floating point unit, the design simplicity, layout regularity and low layout area make this method popular in embedded application. Based on the development of the embedded coprocessor LSC87, the radix 4 SRT algorithm of the implementation for the combination of division and square root is discussed in this paper. The validity of the uncertain region according to the SRT selection constant is verified and the on the fly conversion of redundant iteration result is designed. The designed radix4 SRT parameters can be applied to the combined two arithmetic calculations. By keeping the general datapath, the shared SRT lookup table could simplify the coprocessor control and decrease the overall iteration steps.

在浮点处理元中串行实现除法和平方根计算虽然速度慢 ,但设计简单规则 ,占用资源少 ,有利于嵌入式的应用 .结合嵌入式协处理器 L SC87的研制 ,给出了串行实现除法和平方根计算的基 4SRT算法 ,介绍了确定 SRT选择常数过程中不确定区域的验证方法 ;给出了除法与平方根计算可共用的基 4SRT查询表设计 ;同时讨论了迭代冗余结果向非冗余二进制的转换 .本协处理器设计最大限度地利用了通用数据路径来完成 SRT算法的实现 ,节约了设计资源 ,并缩短了迭代时间

 
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