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电路网表
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  “电路网表”译为未确定词的双语例句
     Research on Netlist Optimization of Asynchronous Combinational Logic Circuits
     异步组合电路网表优化的研究
短句来源
     The synthesizing of the USART based on ASIC, the mapping on technology library, the simulation and verification of circuit based on net table have been done, the logic synthesizing and time analysis verification of the ASIC post-design have been studied.
     完成了该USART串口基于ASIC的电路网表综合、基于网表的电路仿真验证,对ASIC后端设计中的逻辑综合和时序分析验证进行了研究。
短句来源
     PLS: an Automatic Layout Synthesis System for standard cell library is presented in this paper. In this tool, input is the netlist of cell circuits and output is the layout in CIF format. We discuss the layout style employed by PLS and address it's different from the traditional style.
     文章介绍了一种标准单元版图综合工具(cell layout synthesis system),这是一种完全自动化的EDA工具,它能根据输入的单元电路网表和设计规则及单元库高度等参数自动生成符合设计要求且满足设计规则的单元版图。 系统采用了改进的布图模式,得出了面积和电性能更加优化的单元版图。
短句来源
     Simulation of digital circuits is based on computing of logic and delay for component in circuit netlist, so for obtaining correct simulation result, I must have logic computing correctly and delay analysis accuracily.
     由于数字电路的模拟是基于对电路网表中的元件进行逻辑和延时计算的,所以要想得到正确的模拟结果,必须进行正确的逻辑运算和准确的延时分析。
短句来源
     The behavioral model is verified and used in DC/DC power converter system simulation by the tool of Cadence Spectre.
     利用Cadence Spectre仿真器对电路网表和行为模型进行了功能验证和系统级仿真。
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  相似匹配句对
     Research on Netlist Optimization of Asynchronous Combinational Logic Circuits
     异步组合电路网表优化的研究
短句来源
     Basic Direct Current Circuits
     直流电路
短句来源
     Communication Circuits
     通信电路
短句来源
     Research and realization of circuit netlist of electrotechnical and electronic lab in internet
     网上电工电子实验室电路网表问题研究与实现
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This report describes a layout synthesis system called AISCE. The system accepts structural or logic hardware design specification and creates physical layout of integrated circuit automatically. AISCE contains several parts: schematic capture system, netlist compiler, module generators for data and control path, tools for floorplanning, placement and routing, simulators and verifiers, etc.. They are all integrated into one design framework. Following AISCE's synthesis flow, this paper introduces each part of...

This report describes a layout synthesis system called AISCE. The system accepts structural or logic hardware design specification and creates physical layout of integrated circuit automatically. AISCE contains several parts: schematic capture system, netlist compiler, module generators for data and control path, tools for floorplanning, placement and routing, simulators and verifiers, etc.. They are all integrated into one design framework. Following AISCE's synthesis flow, this paper introduces each part of the system. Experimental results show that AISCE is an efficient and promising system.

本文从设计思想和实现路线两方面介绍了一个超大规模集成电路的自动化设计系统-AISCE系统。这是一个结构级版图自动综合系统,针对不同的设计,可以采用结构级硬件描述语言对电路进行描述,并通过优化和综合自动产生最终版图;也可以通过逻辑图编辑器对电路进行交互式编辑或通过输入电路网表对电路进行版图综合产生最终版图。对系统实际使用的验证表明,该系统具有较高的执行效率和广泛的应用前景。

The paper presents an automatic module layoutgenerator with Peripheral constraints (AMGC). Theinput of AMGC is a netlist of the module circuits' Theoutput will be the CMOS layout data of the module'The generated layout meets user's design rule as wellas the peripheral constraints, such as pin POSition andaspect ratio.

本文介绍了一个具有边界约束的大规模集成电路模块版图自动生成系统(AMGC)。AMGC的输入为模块的电路网表,输出为模块的CMOS版图数据。由AMGC自动生成的版图既符合用户的设计规则,也符合模块输入输出端口位置及长宽比等用户给出的约束条件。

Based on the circuits netlists or Boolean expression, parallel constructing is proposed for BDD. In order to traverse state of STG, implicit traversing method is described also. Finally, dynamic adjust approachs that used in the bus-multi CPU system has been discussed.

随着电路规模的迅速增长,设计验证越来越复杂,从而需要高速的数据处理系统。基于总线型多机系统环境,研究电路网表和布尔表达式的BDD(Binary Decision Diagram)并行构造方法,并通过隐含遍历任务的动态调度设计有效地完成时序逻辑的状态遍历。

 
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