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记忆元件
相关语句
  memory element
     A MAXIMUM STRAIN MEMORY ELEMENT
     最大应变记忆元件
短句来源
     The S-iineshape parameter of positron annihilation Doppler-broadening is strongly related to the amount of reversible shape change for a Ti-51.0 at% Ni alloy under constrained aging at different temperatures, showing that the amount of "defects" is an important factor for controlling the performance of two-way shape memory element in the alloy.
     测量了不同温度强制时效后,Ti-51.0 at%Ni合金的正电子湮没Doppler展宽能谱线形S参数,及相应试样的可逆形状变化,发现两者有明显的对应关系,表明“缺陷”量是双向记忆元件性能的一个重要控制因素。
短句来源
     This paper presents a synthesis of synchronous dynamic sequential circuits (SDSC) in which capacitor is used as memory element instead of flip flop for double edge trigger.
     本文提出用电容代替触发器作为记忆元件的双边沿同步动态时序电路(SDSC)的综合方法.基于电路三要素(信号、网络和负载)理论,首先推导出边沿取样定理;
短句来源
  memory elements
     Plateau effect of CuZnAl memory elements
     CuZnAl记忆元件的“台阶”效应
短句来源
     In the implementation, memory elements are not restricted to delay elements or D flip-flops and various standard flip-flops can also be used.
     实现中容许使用各种触发器作记忆元件,而不仅只限于延迟元件或D触发器。
短句来源
  “记忆元件”译为未确定词的双语例句
     The fatigue life gauge is a resistance-fatigue response sensor.
     疲劳寿命计是电阻—疲劳响应记忆元件,其电阻值随疲劳而增加,载荷卸除后电阻变化值保留。
短句来源
     The least plug—in position of memory ceils Can be determined directly in X—D diagram.
     该方法可在 X—D线图上直观地确定记忆元件的最少插入位置数及其插入顺序;
短句来源
     The design method for shape memory spring is discribed by using G-T curves or relationship between τ-γ curves and temperatures of the alloy. The way to deal with the common problems in design is mentioned as well. It is suggested that Cu-base shape memory device may work in the half-thermal-cycling state where stress-induced martensite reversion attributes to shape memory effect.
     介绍了根据记忆合金G-T曲线和τ-γ曲线随温度变化关系设计记忆弹簧元件的方法,并对设计中的常见问题提出了对策,建议Cu基记忆元件应工作在应力诱发马氏体相变的半循环状态下,且应变限制在0.5%以内。
短句来源
     Mathemettcal model of capacitance and inductance are Very different from volt-ampere characteristic the response and excitatance relationship between these two elements are not instantaneous, so they are called memorial elements.
     电容、电感的数学模型和伏安特性不同,这两种元件的电路响应和激励关系是“非即时”的,故为记忆元件.
短句来源
     The paper provided a method of double-quick designing trapezium diagrams of programmable controller,and its key problem was how to switch the three design bases to program diagrams or how to use a diagram to describe the three essential factors of the electrical command unit,checkup unit,executive unit and middle-memory unit in a work cycle.
     提供了可编程控制器控制梯形图的一种快速设计方法,它的关键是如何将三大设计依据转换为程序图,或者说如何用一个图形来描绘电气主令元件、检测元件、执行元件、中间记忆元件在一个工作循环中的动作三要素。
短句来源
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  相似匹配句对
     A MAXIMUM STRAIN MEMORY ELEMENT
     最大应变记忆元件
短句来源
     Plateau effect of CuZnAl memory elements
     CuZnAl记忆元件的“台阶”效应
短句来源
     MEMORY OF COLOURS
     多彩的记忆
短句来源
     Roaming About In My Memories
     记忆漫步
短句来源
     Introduction on Z-Cell
     Z-元件介绍
短句来源
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  memory element
A new memory element based on silicon nanoclusters in a ZrO2 insulator with a high permittivity for electrically erasable read-o
      
Memory element based on Si/CaF2 periodic nanostructures
      
A memory element based on a Si/CaF2 periodic nanostructure is proposed.
      
A model of a soliton-memory element based on a semiconductor superlattice
      
A new type of memory element that records data in the form of electromagnetic solitons is proposed.
      
更多          
  memory elements
Examples of such neurons based on memory elements with optimal parameters are given.
      
Single-crystal Si-α-C : H film heterostructures can operate as photodiodes, photovaractors, and dynamic memory elements.
      
Bifurcations in such systems may provide the possibility of creating new types of memory elements.
      
It is shown that both Si/CaF2-based logical elements and memory elements proposed operate at temperatures from 77 to 300 K, have a switching time of 10-12-10-10 s, and are compatible with silicon IC technology.
      
It is demonstrated that such holograms can be used to construct high-capacity memory elements.
      
更多          
  memory unit
Here we show that human subjects learn a visuomotor sequence by spontaneously chunking the elementary movements, while each chunk acts as a single memory unit.
      
The results suggest that each cluster is processed as a single memory unit, a chunk, and is necessary for efficient sequence processing.
      
Associative information recall is demonstrated for the Marr's memory unit and expressions are derived for an information-content estimation based on parameter values obtained by simulation.
      
Motor programme information as a separable memory unit
      
Two experiments produced further evidence for the claim that motor programme information may be considered as a separate memory unit, partially independent of other memory representations.
      
更多          


In this paper an algorithm is presented. It can assist in developing the near-optimal state assignment for an economical circuit. The storage elements chosen for the design are also shown.

本文提出同步时序电路的通用状态分配。它同时选取优化的状态分配和合适的记忆元件,使电路实现的硬件尽可能少。

In this paper a new logical design methodology is investigated. Being capable of passing by the flow table with its subsequent reduction and coding as the classical method required, one implements directly the explicit equations of predicate calculus t formulas on synchronous sequential circuits. In the implementation, memory elements are not restricted to delay elements or D flip-flops and various standard flip-flops can also be used. Presented first is a general implementation method and then some specificimplementation...

In this paper a new logical design methodology is investigated. Being capable of passing by the flow table with its subsequent reduction and coding as the classical method required, one implements directly the explicit equations of predicate calculus t formulas on synchronous sequential circuits. In the implementation, memory elements are not restricted to delay elements or D flip-flops and various standard flip-flops can also be used. Presented first is a general implementation method and then some specificimplementation techniques are studied.

本文探讨了直接实现(不经过流程表及其简化、编码等手续)谓词演算t式显式方程组成同步时序线路的逻辑设计方法。实现中容许使用各种触发器作记忆元件,而不仅只限于延迟元件或D触发器。先论述一般实现方法,后探讨各种特殊的实现技术。

In this paper the constrution method and function of the multi-input paralleladdition network with the ROM table look-up method are presented.First,a counter-ROM without carry,and with capability of direct processing two's complement isintroduced.Then,the Multi-input parallel addition network construction algorithm basedon counter-ROMs is presented.Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.The Multi-input pa allel addition network proposed here has...

In this paper the constrution method and function of the multi-input paralleladdition network with the ROM table look-up method are presented.First,a counter-ROM without carry,and with capability of direct processing two's complement isintroduced.Then,the Multi-input parallel addition network construction algorithm basedon counter-ROMs is presented.Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.The Multi-input pa allel addition network proposed here has a very flexiblehardware configlaration and offers an extremely high throughput rate.

随着集成电路的飞跃发展,有可能用记忆元件来实现运算电路。本文提出,用ROM(Read—Only Memory)做为运算单元的多输入并行加法网络的构成方法。首先,提出能够处理补码的并行计数器ROM。其次,提出用计数器ROM 作为基本组成单元的多输入并行加法网络的构成算法。最后,推导求出多输入并行加法网络所需的ROM 数的公式,并对影响速度的级数进行讨论。本文提出的多输入并行加法网络有对于任何加权(Weight)的输入都可以进行高速处理的特长。因此,这种电路很适合于高速乘一加运算电路和卷积运算电路,以及高速数字滤波器电路。

 
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