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取数时间
相关语句
  access time
     Main performances are as follows: access time from RAC tRAc≤200ns (335ns, cycle);
     该电路采用3.0微米HMOS技术,其主要性能为:行取数时间tRAc≤200ns(周期为335ns);
短句来源
     CMOS/SOI 4Kb SRAM adopts 1K×4 asynchronous system. So it achieves the fast access time of 30ns with chip size of 3 6mm×3 84mm.
     CMOS/ SOI 4 Kb静态随机存储器采用 1K×4的并行结构体系 ,其地址取数时间为 30 ns,芯片尺寸为 3.6 mm× 3.84 m m ;
短句来源
     An optimized design of embedded 512×8 SRAM which bases on UMC 0.35 μm technics for speed-raising and power-dissipation-saving is presented. It's address access time less than 6ns.
     本文设计了512×8 SRAM(静态随机读写存储器),设计基于UMC 0.35工艺,地址取数时间小于6ns。
短句来源
     To reduce power and im prove the speed of circuit,the stati c RAM' s uses Double -Word -Line,Address -Transition -Detecti on and two stage amplifier technologies,so it achieves the fast access time:30ns.
     为了提高电路的速度和降低功耗,采用地址转换监控Address-Translate-Detector(ATD)、两级字线Double-Word-Line(DWL)和新型的两级灵敏放大等技术,其地址取数时间为30ns,最小动态工作电流为30mA(工作电压5V,工作频率2MHz),静态维持电流为1mA。
短句来源
     The results of CAD circuitssimulation are quite close to these of testing. The access time is 120 ns and the power dissipa-tion is 150 mW.
     用CAD电路模拟的结果与实测十分接近,取数时间为120ns,工作功耗为150mW.
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  “取数时间”译为未确定词的双语例句
     Based on TSMC 0.25 μm technics,the area of a 128 KB SRAM is 0.71 mm×4.6 mm; the time of data-read is 3.091 ns; the dissipation power is 37.985 mW with the frequency of 125 MHz.
     经过仿真验证,采用TSMC0.25μm工艺设计的128KBSRAM芯片面积为0.71mm×4.6mm,取数时间3.091ns,在125MHz工作频率下功耗为37.985mW。
短句来源
     Optimized BES Data Taking Time
     最优化的北京谱仪取数时间
短句来源
     For current ψ′ data taking,the optimized data taking time is 3-5 hours.
     将这个模型应用于目前正在进行的 ψ′数据采集 ,给出了最优化的北京谱仪取数时间 ,使得在同样的运行条件下 ,可以尽可能多地采集到对物理有意义的数据 .
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  相似匹配句对
     Time
     时间
短句来源
     Time is...
     时间
短句来源
     Optimized BES Data Taking Time
     最优化的北京谱仪取数时间
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  access time
According to theoretic analysis and experimental test, we find that RAID5 access time and data transfer rate could be largely improved than conventional method.
      
By using an intelligent cache to control the metadata system, MICC can deal with different scenarios such as splitting and merging of queries into sub-queries for available metadata sets in local, in order to reduce access time of remote queries.
      
We compute the distribution of connected subgraphs visited by an ensemble of walkers, the average access time and survival probability of the walks.
      
For β≥ 3, corresponding to the world-wide Web, the access time of the walk to a given level of hierarchy on the graph is much shorter compared to the standard random walk on the same graph.
      
The number of axes selected represents a trade-off between access time and storage overhead, as more axes usually lead to better filtering but require more overhead to store the associated access structures.
      
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A high speed ECL 256 word by 1 bit RAM has been developed.The typicaladdress access time and read/write cycle time are 12 and 22ns,respectively,withthe power dissipation of 500mW.The dependence of electrical performance on thetemperature and power supply voltage is given.The devices can operate over thewide range of T_a=-55-+150℃ and V——(EE)=-3.5--7.0 V. The main characteristics of the circuits and mask design as well as the fabri-cation technology and device structure are mentioned in this paper.

高速 ECL 256字×1位随机存储器是在改进设计以及采用漂发射区、双层金属布线等工艺基础上得到的.地址取数时间典型值为12毫微秒,读写周期为22 毫微秒,功耗500毫瓦,可靠性高、这个器件能在环境温度-55-+150℃以及电源电压-3.5—-7.0伏范围内正常工作. 本文介绍了在线路和版图设计以及制造工艺方面的特点.

A 1024 word ×1 Bit ECL RAM has been developed with the major electrical charac-teristics summarized as follows.The typical address access time and minimum write pulsewidth are less than 20 ns and 10 ns,respectivel,under 500 m W power dissipation (V_(EE)=-5V). The ambient temperature is allowel to change within T=55-125℃,and supplied voltage, V_(EE)=4--6V.The naximum address access time of 25 nscan be obtained up to T-85℃. A chip size of 11.4mm~2 has been realized adopting4 μm design rule.The device circuits,technology...

A 1024 word ×1 Bit ECL RAM has been developed with the major electrical charac-teristics summarized as follows.The typical address access time and minimum write pulsewidth are less than 20 ns and 10 ns,respectivel,under 500 m W power dissipation (V_(EE)=-5V). The ambient temperature is allowel to change within T=55-125℃,and supplied voltage, V_(EE)=4--6V.The naximum address access time of 25 nscan be obtained up to T-85℃. A chip size of 11.4mm~2 has been realized adopting4 μm design rule.The device circuits,technology and characteristic performance aredescribed in this paper.

研制成功的 ECL 1024字 ×1位随机存储器的地址取数时间为 20ns、功耗 500mW、芯片面积 11.4mm~2.它是高速电子计算机不可缺少的关键性器件.采用 4μm设计原则以及薄外延层、浅结、漂发射区和双层金属有线等工艺。本文报道了设计、工艺以及性能特点.

A high performance 16 K (2K×8) NMOS-SRAM is designed and fabricated using doublepoly-si NMOS technology based on the 3 μm design rule.The chip architecture,memory cell,sense amplifier and decoder circuits are analysed and optimized.The results of CAD circuitssimulation are quite close to these of testing.The access time is 120 ns and the power dissipa-tion is 150 mW.

本文描述一种性能较好的16K(2K×8)NMOS-SRAM的设计.该电路采用3μmNMOS双层多晶硅工艺进行制作.对它的结构、存贮单元、灵敏读出放大器以及译码电路等进行了分析和优化.用CAD电路模拟的结果与实测十分接近,取数时间为120ns,工作功耗为150mW.

 
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