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地址运算
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  address calculation
     It's a tackle that address calculation of array name for C language. Thispaper expound a new concept, emphasis of this concept is definition of wide array dimension, and this definition apply in address calculation of array name, resolved this tickler successfully.
     C语言中的数组名的地址运算是一难点.作者通过提出一种新概念,成功地解决了这一难点.此概念的重点是广义数组维数的定义,以及它在数组名地址运算中应用
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  “地址运算”译为未确定词的双语例句
     SMDSP is a high performance 32-bit floating-point Digital Signal Processor developed for special application. SMDSP CPU consists of ALU? Multiplier?
     SMDSP是针对专门应用开发的高性能32位浮点数字信号处理器,其CPU内有独立的ALU、乘法器、数据地址产生器和六条局部数据总线,实现了乘加运算并行,算术运算与地址运算并行,加快了数据处理速度。
短句来源
     In this paper, a novel algorithm of LS-DSP AGU is proposed by studying DSPA address computation character.
     本文通过研究常用的数字信号处理计算的数据地址运算特点,提出了LS-DSP地址产生器的生成算法。
短句来源
     The RISC processorwith AG(Address Generator,AG) can realize the operations of arithmetic and address in parallel,which improve the performance of RISC processor.
     在RISC处理器中设计独立的地址产生器可实现算术运算与地址运算并行处理,从而提高RISC处理器的性能。
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  相似匹配句对
     Understanding Internet Addresses
     INTERNET地址
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     Moral Operation
     道德运算
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     IP ADDRESS
     IP地址
短句来源
     The Operation Properties of Adjoint
     伴随矩阵的运算性质
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  address calculation
A data model for the analysis of worst and expected case performance of order preserving address calculation type data structures is presented.
      
Compilation Methods for the Address Calculation Units of Embedded Processor Systems
      
For the required level of memory interaction, the parallel executing Address Calculation Unit (ACU) is often used to tune the architecture to the memory access characteristics of the application.
      
While software schemes require less hardware support than hardware schemes, they must generate address calculation instructions and a prefetch instruction for each datum that needs to be prefetched.
      
These instructions may then communicate prior to address calculation and disambiguation via a fast communication mechanism.
      
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  address arithmetic
Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures
      
In these DSPs, an indexed addressing mode is generally not available, so automatic variables must be accessed by allocating address registers and performing address arithmetic.
      
Subsuming address arithmetic into auto-increment /decrement arithmetic improves both the performance and size of the generated code.
      
Thus, the optimization techniques in a compiler can be used not only to generate efficient or compact code, but also to help the designer of a custom DSP architecture make decisions on address arithmetic features.
      
However, care must be taken in the ordering of IR statements and translation of implicit address arithmetic.
      
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In the first part of this paper, an analysis of the characteristics of data schedule under nested loops is presented. Three aspects which include the significance of the fulfillment of data accessing by the address counter, the principles of ILSP (interlaced inner and outer loop software pipelining) algorithm and under the idea of ILSP algorithm are presented. And a discussion of the data scheduling characteristics is given. In part 2, the key steps of how to derive the data addressing control sequence from...

In the first part of this paper, an analysis of the characteristics of data schedule under nested loops is presented. Three aspects which include the significance of the fulfillment of data accessing by the address counter, the principles of ILSP (interlaced inner and outer loop software pipelining) algorithm and under the idea of ILSP algorithm are presented. And a discussion of the data scheduling characteristics is given. In part 2, the key steps of how to derive the data addressing control sequence from the applications is listed. In part 3 and part 4, the authors respectively discuss how to apply the sequence of data accessing control to control the address counter and how to simplify the data accessing control sequence to the reduced data accessing control sequence. The part 5 is experiment results and part 6 is conclusion.

文章第1节对软件流水下多重循环中数据元素的调度进行了分析,着重讨论了用地址计数器完成简单地址运算的意义、ILSP(interlacedinnerandouterloopsoftwarepipelining)算法的基本思想及其在此基础上分析了软件流水下多重循环中数据元素的调度特点;第2节进一步探讨了为完成调度而寻找地址控制信息序列的一般方法;第3、4节则分别讨论了用求得的地址控制信息序列控制地址计数器对数据元素的访问和将地址控制信息序列化简为精简地址控制信息序列的步骤;最后两节分别是实验结果和结论

It's a tackle that address calculation of array name for C language. Thispaper expound a new concept, emphasis of this concept is definition of wide array dimension, and this definition apply in address calculation of array name, resolved this tickler successfully.

C语言中的数组名的地址运算是一难点.作者通过提出一种新概念,成功地解决了这一难点.此概念的重点是广义数组维数的定义,以及它在数组名地址运算中应用

SMDSP is a high performance 32-bit floating-point Digital Signal Processor developed for special application. SMDSP CPU consists of ALU?Multiplier?Address Generator and six local data buses, which can carry out not only Addition and Multiplication but also Arithmetic and Address operation in parallel, so it accelerates processing speed obviously. SMDSP can be used in DSP system conveniently and efficiently by the design of Sequential ? Bit-Reversed and Circular addressing mode. SMDSP is fabricated in a 0.5um...

SMDSP is a high performance 32-bit floating-point Digital Signal Processor developed for special application. SMDSP CPU consists of ALU?Multiplier?Address Generator and six local data buses, which can carry out not only Addition and Multiplication but also Arithmetic and Address operation in parallel, so it accelerates processing speed obviously. SMDSP can be used in DSP system conveniently and efficiently by the design of Sequential ? Bit-Reversed and Circular addressing mode. SMDSP is fabricated in a 0.5um three-mental CMOS process, the area is 6.2×6.7mm2, and the operation frequency is 50MHz.

SMDSP是针对专门应用开发的高性能32位浮点数字信号处理器,其CPU内有独立的ALU、乘法器、数据地址产生器和六条局部数据总线,实现了乘加运算并行,算术运算与地址运算并行,加快了数据处理速度。数据地址产生器支持顺序、倒位序、循环三类数据地址的计算,使得SMDSP能方便高效地应用于数字信号处理系统。

 
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