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二进制输出
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  binary output
    The interface agreement of digitizer is discussed. The (SUPER) driver programming methods based on ASCII and binary output formats are recommended.
    本文首先讨论了数字化仪的接口数据协议,然后介绍了基于 ASC Ⅱ输出格式和基于二进制输出格式的驱动程序设计方法。
短句来源
    When user set VB picture box by ScaleWidth and ScaleHeight and drews graphics in the picture box by mouse action, the Y coordinate of the mouse would be used as binary output of the arbitrary wave generator.
    用ScaleWidth和ScaleHeight属性设置VB刻度时,可将移动鼠标到图片框,以鼠标Y坐标值作为任意波形发生器的二进制输出值。
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    The high-resolution position data in the centimeter grade are extracted from the binary output records of the hand-held GPS position indicator,and the multiple average measurement and post-operation position difference correction method are used so as to decrease the planar locating error of the portable and cheap hand-held GPS position indicator from several meters to 1 m or so. Thus the precision of the sub-meter grade can be attained.
    从手持GPS定位仪的二进制输出记录中提取出厘米级的高分辨率位置数据,并使用多次平均值测量、位置后差分校正的方法,使轻便、价廉的手持GPS定位仪平面定位误差从数米降低到1 m左右,达到亚米级精度。
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  “二进制输出”译为未确定词的双语例句
    The experimental results show that the output representation is also important for the network performance. In particular, for our example, the binary approach works much better than the other two.
    测试结果表明输出表示的研究对BP网络的性能也非常重要,特别地,二进制输出表示法比其他两种方法有更好的效果。
短句来源
    The simulation results demonstrate that the power dissipation of the converter is less than 300mW for 5V supply and the signal bandwidth is about 80MHz. The latency between input and output is 2.5 clock cycles.
    仿真结果 :采样频率为 2 5 0 Ms/s时 ,功耗小于 30 0 m W,输入信号带宽约 80 MHz,输入模拟信号和二进制输出码输出之间延迟为 2 .5个时钟周期
短句来源
    Simulation results show the converter consumes 120mW from a 5V supply. The delay between input signal and output code is 2.5 clocks. The chip occupies 1.44mm 2.
    在5V电源电压下 ,仿真结果为 :当采样频率为 5 0MSPS时 ,功耗为 12 0mW ,输入模拟信号和二进制输出码之间延迟为2 5个时钟周期 ,芯片面积 1 4 4mm2 .
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  binary output
The capacity of a channel with arbitrarily varying channel probability functions and binary output alphabet
      
with binary output in a number of cases, essentially with the aid of a lemma which relates the capacity of the a.v.ch.
      
We are thus able to extend certain results given for binary output a.v.ch.
      
Neural networks have been used to 'clone' this expertise but these applications have used small numbers of sensors, and their structure has used a binary output, giving rise to possible controller oscillations.
      
We study statistical tests with binary output that rarely outputs one,
      
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The interface agreement of digitizer is discussed. The (SUPER) driver programming methods based on ASCII and binary output formats are recommended.

本文首先讨论了数字化仪的接口数据协议,然后介绍了基于 ASC Ⅱ输出格式和基于二进制输出格式的驱动程序设计方法。

A 150Msamples/s,6bit CMOS folding and current mode interpolating analog to digital is designed in a 1 2μm digital CMOS technology.A low power,high speed regenerated current comparator is proposed.By adopting Domino logic circuit,a very simple and flexible decoder is realitied with high speed and low power.The latency between input signal and output code is less than 2 clock cycles.The ADC only uses a single clock and its complement which simplifies the whole circuit.The converter power dissipation is simulated...

A 150Msamples/s,6bit CMOS folding and current mode interpolating analog to digital is designed in a 1 2μm digital CMOS technology.A low power,high speed regenerated current comparator is proposed.By adopting Domino logic circuit,a very simple and flexible decoder is realitied with high speed and low power.The latency between input signal and output code is less than 2 clock cycles.The ADC only uses a single clock and its complement which simplifies the whole circuit.The converter power dissipation is simulated as 185mW from a 5V supply.

在 1.2μm SPDM标准数字 CMOS工艺条件下 ,实现 6 bit CMOS折叠、电流插值 A/ D转换器 ;提出高速度再生型电流比较器的改进结构 ,使 A/ D转换器 (ADC)总功耗下降近 30 % ;提出一种逻辑简单易于扩展的解码电路 ,以多米诺 (Domino)逻辑实现 .整个 ADC电路中只使用单一时钟 .在 5 V电压条件下 ,仿真结果为采样频率 15 0 -Ms/ s时功耗小于 185 m W,输入模拟信号和二进制输出码之间延迟小于 2个时钟周期 .

A master-slave T/H circuit with the offset compensative amplifiers is proposed,which can improve sample precision and input bandwidth.A 250Ms/s,6-bit CMOS folding and interpolating A/D converter with M-S T/H is designed in a 1.2μm standard digital CMOS process.The simulation results demonstrate that the power dissipation of the converter is less than 300mW for 5V supply and the signal bandwidth is about 80MHz.The latency between input and output is 2.5 clock cycles.

提出了一种主从式 T/H电路 ,有效解决了折叠 ADC预处理器限制输入信号带宽的问题 ,使预处理电路速度及稳定性得到大幅度改善 ;同时该 T/H结构使用内部差分误差补偿技术 ,在高采样率情况下保持良好的精度 ,有效抑制了电荷注入、时钟馈通等问题 .在 1 .2 μm SPDM标准数字 CMOS工艺条件下 ,实现 6 bit CMOS折叠、电流插值 A/D转换器 .仿真结果 :采样频率为 2 5 0 Ms/s时 ,功耗小于 30 0 m W,输入信号带宽约 80 MHz,输入模拟信号和二进制输出码输出之间延迟为 2 .5个时钟周期

 
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