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缓冲模块
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  buffer module
     The corresponding driver module and buffer module are appended in the route of data flow to avoid data conflict and ensure data integrality.
     在数据流的路径上添加了相应的驱动和缓冲模块,避免了冲突,保证了数据的完整性。
短句来源
     In this method argues that singals be divided into several types and can use a kind of buffer module in the design.
     在减少应答/请求信息和数据通讯量方面提出了将系统传输数据分类和采用数据缓冲模块的设计方法。
短句来源
     3. Successfully designed the buffer module in the“CFHC IP Core”project. The module is based on the architecture of two symmetrical asynchronous FIFOs to transmit data in and out separately to the purpose of transmit and buffer data and change the bit of data width.
     3、成功设计了“CF卡控制器”IP核中的数据缓冲模块在本设计中使用了以两个协同对称的异步FIFO为基础构成的数据缓冲模块来实现CFHC(Compact Flash card Host Controller)IP核的数据位宽转换、缓冲存储及传输等任务。
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  “缓冲模块”译为未确定词的双语例句
     As the core technology of OFDM, FFT module is designed with the IP Core of which the interface follows ALTERA Atlantic protocol.
     然后对OFDM核心部分的FFT算法进行FPGA的IP Core设计实现,严格按照ALTERA Atlantic接口协议实现了IP Core的接口控制器,同时实现了QAM映射器、循环前缀、加窗处理和乒乓操作的RAM缓冲模块
短句来源
     4. There are three communication agreements designed here, which including the data exchange agreement between the principal CPU and the subordinate CPU, the agreement between the general control CPU and the touchscreen, the agreement between the principal machine and the sub-machine.
     4.设计了三套通讯协议,包括下位机子站中主从CPU通过数据缓冲模块进行数据交换的通讯协议; 主控CPU与触摸屏的通讯协议;
短句来源
     The part of hardware includes mainly the module of image acquisition, the module of video A/D, the module of image buffer, the module of interface logic control, the module of image processing based on DSP and the module of power management. The hardware modules accomplish the image acquisition, digitization, buffer and processing.
     硬件部分主要包括图像采集模块、视频A/D模块、图像数据缓冲模块、接口逻辑控制模块、基于DSP的图像处理模块和电源管理模块等,实现了图像信号的采集、数字化、缓冲和处理。
短句来源
     The system includes four blocks: CCD driving, data acquisition, data buffering and date processing.
     该数据采集系统可以分为CCD驱动模块、数据采集模块、数据缓冲模块和数据处理模块四个部分。
短句来源
     For high speed A/D conversion with Delphi, a double exchange buffers is designed to store sample data.
     为了保证数据采集的高速有效 ,文章介绍了一种双缓冲模块交替工作的程序。
短句来源
  相似匹配句对
     The X modules
     X模块技术
短句来源
     Boards & Modules
     电路板和模块
短句来源
     BUFFER CAPACITY
     缓冲容量
短句来源
     Network Transmission Module Base on Multi-buffer and Multithreading in Distributed Simulation System
     分布式仿真中多缓冲多线程网络模块的设计
短句来源
     The Buffer of On-board Test Circuit Module in High g Shock
     高g值冲击下存储测试电路模块缓冲保护研究
短句来源
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  buffer module
The loop buffer module used in this switch architecture is a new approach towards WDM buffering of packets.
      
A grant signal is also sent to the grant port of the buffer module Buf I, leading to the read port of the buffer module activated.
      
During the last user's stream, the estimated received signal is passed to the revised signal buffer module rather than being stored in local RAM.
      
For many applications this buffer module is an ideal and cost effective alternative to a battery based backup system.
      
For example, a typical buffer module has ports corresponding to read/write ports, and parameters such as buffer size and width.
      
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The mechanical environment where the airbrone electronic equipment is in are more complicated and unfavourable. How to slove them reasonably is key to improving equipment's energy of guarding against virbration &. resisting lash, and making it adjust to all kinds of virbration &. lash environment, such as the equipment s entirety arragnment, construction entirety design, installation of heart and parts, virbration isolating &. lash relaxing module design, ect. This paper explains some equestions stated above...

The mechanical environment where the airbrone electronic equipment is in are more complicated and unfavourable. How to slove them reasonably is key to improving equipment's energy of guarding against virbration &. resisting lash, and making it adjust to all kinds of virbration &. lash environment, such as the equipment s entirety arragnment, construction entirety design, installation of heart and parts, virbration isolating &. lash relaxing module design, ect. This paper explains some equestions stated above combined with specific practice.

机载电子设备所处的机械环境比较复杂、恶劣,如何合理地解决好设备的总体布局、整机结构总体设计、机芯及元器件的安装以及隔振、缓冲模块设计等问题,对于提高设备的防振动、抗冲击能力.使其能适应B机的各种振动、冲击环境起着关键的作用。本文结合具体实践对上述问题进行了阐述。

Delphi is an excellent program tools that supports object oriented design. But it cannot operate in low layer such as hard interrupt. Hard interrupt can be realized by VxD technology, which is a key method to realize real time data sample in Windows 95. A new method use DLL and VxD by Delphi to sample data with hard interrupt is described in this paper. The design technique and the link method of VxD and DLL are presented. For high speed A/D conversion with Delphi, a double exchange buffers is designed to...

Delphi is an excellent program tools that supports object oriented design. But it cannot operate in low layer such as hard interrupt. Hard interrupt can be realized by VxD technology, which is a key method to realize real time data sample in Windows 95. A new method use DLL and VxD by Delphi to sample data with hard interrupt is described in this paper. The design technique and the link method of VxD and DLL are presented. For high speed A/D conversion with Delphi, a double exchange buffers is designed to store sample data. It can improve the speed of A/D conversion in Windows95 and make system works in real time.

Delphi是一种优秀的面向对象的编程工具 ,但 Delphi不能直接实现诸如硬件中断等底层操作 ,硬件中断可采用 Vx D技术。采用 Vx D编程是在 WIN95下实现实时数据采集的关键技术。本文提出了用 Delphi结合 DL L和 Vx D技术 ,通过中断实现 A/ D转换的方案 ,文中阐述了 Vx D和DL L的设计过程 ,Delphi和 DL L的连接方法。为了保证数据采集的高速有效 ,文章介绍了一种双缓冲模块交替工作的程序。利用这种方法可以提高数据采集的精度和速度 ,满足实时性的要求。

Discussed MPLS signaling protocols, methods of mapping IP routing information into ATM labels,and architectures of VC merge capable ATM LSR were discussed. The composing of the output-buffered module and the working process were expatiated. The output buffered module that is capable of implementing VC merging function in output buffered architecture was analyzed deeply. In view of actual intention, the demand to capacity of the extra buffers resulting from VC merging is not large in cell level; VC merging...

Discussed MPLS signaling protocols, methods of mapping IP routing information into ATM labels,and architectures of VC merge capable ATM LSR were discussed. The composing of the output-buffered module and the working process were expatiated. The output buffered module that is capable of implementing VC merging function in output buffered architecture was analyzed deeply. In view of actual intention, the demand to capacity of the extra buffers resulting from VC merging is not large in cell level; VC merging can obtain larger flexibility than the non VC merging can in packet level. The project can provide potential supporting to QoS control by implementing part merging.

论述了MPLS信令协议、IP路由信息映射成ATM标记的方法、可实施VC合并ATM LSR的体系结构 ,阐述了输出缓冲体系结构模型的组成及其工作过程 ,对输出缓冲体系结构模型中执行VC合并功能的输出缓冲模块 (OBM )进行了深入的分析·指出对于最实际的目的而言 ,在信元级 ,由VC合并带来的对附加缓存容量的要求并非很大 ;在包一级 ,VC合并获得了比非VC合并更大的灵活性 ,更重要的是通过实施部分VC合并能够对QoS控制提供很强的潜在支持·

 
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