Study of the New High Performance PCI Express Interconnect Technology
The waveguides(poly Si/SiO_2,Si/SiO_2,Si_3N_4/SiO_2)for on-chip optical interconnect have been analyzed in detail,including the basic conditions,fabrication method and loss mechanism. The recent progress is summarized.
During the electronmigration tests in the range of 3×105 A/cm2 and 4×106 A/cm2 for 275 min, the tensile stress at the anode of Al interconnects changed into the compress stress, which then increased with the increasing of current density.
Analytical-BEM coupling method for fast 3-D interconnect resistance extraction
Deep submicron process technology is widely being used and interconnect structures are becoming more and more complex.
The irradiation provides the Joule heating of narrow and electrically high resistive pore throats, which interconnect cavities within the medium and, consequently, determine the permeability of the medium.
An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits
Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM.
The method cuts selected interconnecting lines then it calculates the resistances of straight sections using an analytical formula and the resistances of the other sections using the boundary element method (BEM).
This suggests that cooling after inserting tellurium results in its directional crystallization, which is possibly controlled by the interconnecting channels.
For T>amp;lt;20 K, κphop (T) is governed by boundary phonon scattering from bottlenecks in horn-shaped channels interconnecting the octahedral and tetrahedral first-order opal voids filled by sodium chloride.
Analysis of the transmission properties of tapered mutliconductor interconnecting buses in high-speed integrated circuits
Analysis approach and formulas for the transmission properties of uniform multiconductor interconnecting buses in high-speed integrated circuits are presented in this article.
Analytical delay models for RLC interconnects under ramp input
Analytical delay models for Resistance Inductance Capacitance (RLC) interconnects with ramp input are presented for different situations, which include overdamped, underdamped and critical response cases.
The value of bend resistance changes in inverse proportion to the width of interconnects and drops with increasing temperature in the range of 4.2-77 K.
The circuit-optimization criterion is the degree of utilization of FPGA logic units and interconnects.
The crosstalk between neighboring interconnects gradually becomes the main noise sources in DSM ICs.