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并行加法网络
相关语句
  parallel addition network
     THE DESIGN OF AN ALL PLA PARALLEL ADDITION NETWORK
     全PLA并行加法网络的设计
短句来源
     PARALLEL COUNTER ROMs AND THEIR APPLICATION FOR THE MULTIPLE PARALLEL ADDITION NETWORK
     并行计数器ROM及其在多输入并行加法网络中的应用
短句来源
     The experimental results indicate that the application of PROM's multiple-input parallel addition network to the high-bit-rate programmable PCM telemetry frame synchronizer is successful.
     系统实验表明,这种PROM化并行加法网络应用于高速可编程PCM遥测帧同步器是行之有效的。
短句来源
     The multiple-input parallel addition network proposed in this paper is not only capable of processing any weight input directly and quickly, but also simple in construction and easy to realize Computer Aided Design (CAD).
     本文提出的多输入并行加法网络不但具有对于任何权(Weight)的输入信号直接进行高速处理的特点,而且,还具有结构非常简单、容易实现计算机辅助设计(CAD)的优点。
短句来源
     A Construction Method for Multi-input Parallel Addition Network With ROMs
     全ROM化多输入并行加法网络
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  “并行加法网络”译为未确定词的双语例句
     Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.
     最后,推导求出多输入并行加法网络所需的ROM 数的公式,并对影响速度的级数进行讨论。
短句来源
     The Multi-input pa allel addition network proposed here has a very flexiblehardware configlaration and offers an extremely high throughput rate.
     本文提出的多输入并行加法网络有对于任何加权(Weight)的输入都可以进行高速处理的特长。 因此,这种电路很适合于高速乘一加运算电路和卷积运算电路,以及高速数字滤波器电路。
短句来源
  相似匹配句对
     THE DESIGN OF AN ALL PLA PARALLEL ADDITION NETWORK
     全PLA并行加法网络的设计
短句来源
     A Construction Method for Multi-input Parallel Addition Network With ROMs
     全ROM化多输入并行加法网络
短句来源
     NETWORK
     网络
短句来源
     Machine Group Network Parallel Computation
     机群网络并行计算
短句来源
     Networking
     网络
短句来源
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In this paper the constrution method and function of the multi-input paralleladdition network with the ROM table look-up method are presented.First,a counter-ROM without carry,and with capability of direct processing two's complement isintroduced.Then,the Multi-input parallel addition network construction algorithm basedon counter-ROMs is presented.Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.The Multi-input pa allel addition network proposed here has...

In this paper the constrution method and function of the multi-input paralleladdition network with the ROM table look-up method are presented.First,a counter-ROM without carry,and with capability of direct processing two's complement isintroduced.Then,the Multi-input parallel addition network construction algorithm basedon counter-ROMs is presented.Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.The Multi-input pa allel addition network proposed here has a very flexiblehardware configlaration and offers an extremely high throughput rate.

随着集成电路的飞跃发展,有可能用记忆元件来实现运算电路。本文提出,用ROM(Read—Only Memory)做为运算单元的多输入并行加法网络的构成方法。首先,提出能够处理补码的并行计数器ROM。其次,提出用计数器ROM 作为基本组成单元的多输入并行加法网络的构成算法。最后,推导求出多输入并行加法网络所需的ROM 数的公式,并对影响速度的级数进行讨论。本文提出的多输入并行加法网络有对于任何加权(Weight)的输入都可以进行高速处理的特长。因此,这种电路很适合于高速乘一加运算电路和卷积运算电路,以及高速数字滤波器电路。

With the fast development of integrated circuits, it is possible to make up an arithmetic circuit with memory elements. In this paper, a scheme for arithmetic circuits using ROMs is investigated. First, the mathematical models of various parallel counter ROMs are presented. Then, the constitution algorithm for multiple-input parallel addition networks with these parallel-counter ROMs is investigated. Finally, the processing time of the multiple-input parallel addition network is discussed.The multiple-input...

With the fast development of integrated circuits, it is possible to make up an arithmetic circuit with memory elements. In this paper, a scheme for arithmetic circuits using ROMs is investigated. First, the mathematical models of various parallel counter ROMs are presented. Then, the constitution algorithm for multiple-input parallel addition networks with these parallel-counter ROMs is investigated. Finally, the processing time of the multiple-input parallel addition network is discussed.The multiple-input parallel addition network proposed in this paper is not only capable of processing any weight input directly and quickly, but also simple in construction and easy to realize Computer Aided Design (CAD). Thus, this type of circuits is very suitable for digital signal processing units.

随着集成电路的飞跃发展,有可能用记忆元件来实现运算电路,本文提出利用ROM(Read only Memory)实现运算电路的一种方法。首先,提出各种并行计数器ROM的数学模型,其次,提出利用这种并行计数器ROM作为基本单元的多输入并行加法网络的构成算法,最后,对影响速度的因素进行讨论。 本文提出的多输入并行加法网络不但具有对于任何权(Weight)的输入信号直接进行高速处理的特点,而且,还具有结构非常简单、容易实现计算机辅助设计(CAD)的优点。因此,这种电路非常适合于高速乘法器、高速乘加器、高速卷积处理器,以及高速数字滤波器等信息处理用运算电路。

This paper presents a new algorithm for the construction of a parallel multiplier with ROMs. Because a multiple-input parallel addition network with ROMs is used as an adder circuit of a part of products instead of the carry-lookahead adder, this multiplier operates much faster than the schemes of Wallace and Dadda. It has many advantages-simple construction, fast operation, and easy realization of LSI and CAD. Therefore, as a new type of operational unit it is worth extending its application in those intelligent...

This paper presents a new algorithm for the construction of a parallel multiplier with ROMs. Because a multiple-input parallel addition network with ROMs is used as an adder circuit of a part of products instead of the carry-lookahead adder, this multiplier operates much faster than the schemes of Wallace and Dadda. It has many advantages-simple construction, fast operation, and easy realization of LSI and CAD. Therefore, as a new type of operational unit it is worth extending its application in those intelligent instrument and digital signal processors.

本文提出全ROM化并行乘法器的构成方法,这种乘法器由于抛弃CLA型加法器,而采用全ROM化多输入并行加法网络作为部分积的加法电路,比Wallace方式和Dadda方式大大提高乘法速度。全ROM化乘法器具有结构简单、速度快、容易实现LSI化和CAD化的优点。因此,作为新型运算部件,在智能化仪器和数字专用处理器中具有极好的推广价值。

 
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