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  double buried
     Double buried layers,N type epitaxial layer,double layers of metal Ti Al and PECVD SiN x are chosen for the technology.
     该工艺采用P型衬底、N型P型双埋层、N型薄外延结构,掺杂多晶硅作为CMOS晶体管栅极和双极NPN晶体管的发射极。
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  “双埋”译为未确定词的双语例句
     Due to high stress between the Si/Si3N4 there is a high interface defectAbstractdensity inherent to silicon nitride interface. We have successfully fabricated SOIM structures with SiO2-Si3N4 as buried insulating films using epitaxial layer transfer technology.
     为避免顶层Si/Si_3N_4界面处存在的高界面态,成功的采用多孔硅外延转移技术制备出以SiO_2/Si_3N_4为双埋层的SOIM新结构,其中二氧化硅作为过渡层。
短句来源
     H+, He co-implantation and Smart-Cut technology were employed.
     设计了H、He共注入,采用Smart一Cut工艺双埋层501基底的制备流程和具体参数。
短句来源
     NPN and CMOS devices have been fabricated on the same chip with a buried twin well and epitaxy structure, using 2μm design rule.
     采用双埋层、双阱和外延结构,应用2μm设计规则,成功地将NPN器件和CMOS器件制作在同一芯片上。
短句来源
     The devices based on new SOIM structure has been verified in two-dimensional device simulation and indicated that the new structures reduce device self-heating effect and increase the drain of the SOI MOSFET. It is the first time that we fabricated SOIM structures with SiO2-Si3N4-SiO2 as buried insulating films using Smart-cut technology.
     为减少双埋层SOIM片的翘曲度及减少这种结构中由于硅衬底与氮化硅直接接触引入的高界面态,首次采用智能剥离技术成功制备出以SiO_2/Si_3N_4/SiO_2为三埋层SOIM新结构,其中的两个二氧化硅埋层均为过渡层;
短句来源
     A 3-um ECL process is adopted to fabricate the device. A maximum operating frequency of 400MHz has been obtained, which is 40 times higher than that for a conventional TTL or CMOS shift register. The temperature range for the device is -55~85C.
     采用单元结构设计方法进行逻辑设计、电路设计、版图设计和整体设计,用3μm双埋层对通pn结隔离ECL技术进行工艺制作,其最高工作频率达到400MHz以上,工作温度范围为-55℃~85℃,比常规的TTL或者COMS移位寄存器工作频率高40倍。
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     A heat transfer model for double U-tube geothermal heat exchangers
     U型管地热换热器的传热模型
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     Dual Lenses
     透镜
短句来源
     Simulation of A Double RESURF LDMOS With P Buried Layer Based on Thin EPI Layer
     薄外延PRESURF LDMOS仿真设计
     adopting the double cantilevers;
     采用腕臂;
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     Buried Resistors
     内电阻
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  double buried
A case of double buried earrings in earlobes: uncommon complication
      
We report a case of double buried earrings in each earlobe in a child with history of 'missing' earrings.
      


A high speed BiCMOS technology for integrated system is described. NPN and CMOS devices have been fabricated on the same chip with a buried twin well and epitaxy structure, using 2μm design rule. Satisfactory characteristics of single device have been achieved. Under heavily loading condition the speed of BiCMOS inverter is much faster than that of ordinary CMOS inverter.

本文描述了一种可用于集成系统的高速BiCMOS技术。采用双埋层、双阱和外延结构,应用2μm设计规则,成功地将NPN器件和CMOS器件制作在同一芯片上。得到了满意的单管性能。在大负载条件下,BiCMOS反相器门的速度比普通CMOS反相器门快得多。

The design of a very high-speed 8-bit shift register and its fabrication process are described in the paper. The cell structure is used for the design of logic,circuit and layout as well as overall planning. A 3-um ECL process is adopted to fabricate the device. A maximum operating frequency of 400MHz has been obtained, which is 40 times higher than that for a conventional TTL or CMOS shift register. The temperature range for the device is -55~85C.

介绍了一种超高速八位移位寄存器的设计和工艺制造技术。采用单元结构设计方法进行逻辑设计、电路设计、版图设计和整体设计,用3μm双埋层对通pn结隔离ECL技术进行工艺制作,其最高工作频率达到400MHz以上,工作温度范围为-55℃~85℃,比常规的TTL或者COMS移位寄存器工作频率高40倍。

A high speed ECL programmable frequency divider is described in the paper.including the design of logic,circuit and layout as well as the temperature compensation considerations.A 4-μm double-layer- buried p-n junction isolation ECL process was used to fabricate the device. An operating frequency above 100MHz has been achieved for the divider,with temperature range in-55~+125℃. The dividing modules are arbitarily variable in natural number between 1~64.

本文介绍了一种ECL高速可编程分频器的逻辑设计、电路设计、温度补偿设计、版图设计及研制结果。采用4μmpn结双埋层对通隔离ECL工艺技术制作的可编程分频器,其最高工作频率达100MHz以上,工作温度范围为-55~+125℃,分频模数在1~64之间任意自然数连续可变。

 
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