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rtl级
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  rtl
     Design and Realization of USB 2.0’s Protocol Layer Based on RTL
     基于RTL级USB2.0协议层的设计与实现
短句来源
     Optimization of Architecture for Viterbi Decoder on RTL Design Stage
     Viterbi解码器RTL级设计优化
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     A 16×16 Bit Signed/Unsigned Synthesizable High-Speed Multiplier in High Level RTL Code
     16×16位带符号/无符号基于RTL级实现的可综合的高速乘法器
短句来源
     A16×16-b Signed/Unsigned Synthesizable High-Speed Multiplier in high-level RTL code
     基于RTL级实现的可综合的16×16位带符号/无符号高速乘法器
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     Test Method of DSP Chip RTL Based on XML
     基于XML的DSP芯片RTL级测试方法
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  rtl level
     The design is described with VerilogHDL at RTL level. Based on Xilinx VertexII xc2v250-6fg256,synthesis are conducted with ISE6.1.
     设计使用VerilogHDL语言在RTL级描述,并以Xilinx VertexII系列中的xc2v250-6fg256器件为基础在ISE6.1下完成综合。
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     Realization of RTL Level Code by FPGA-operated SDRAM
     使用FPGA操作SDRAM的RTL级代码实现
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     We accomplished the RTL level description of the DLX microprocessor core in Verilog, and completed functional verification and pipeline performance analysis on the ModelSim SE 5.6 platform.
     本文使用Verilog硬件描述语言实现了五级静态单流水线结构的DLX微处理器核的RTL级描述,并在modelsim SE 5.6开发平台上对其完成了功能验证和流水线性能分析。
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     The Synthesizability of Verilog HDL at the RTL Level Description
     Verilog HDL语言RTL级描述的可综合性
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     4. The RTL level simulation of the MLB/AHB bridge using Bus Function Model (BFM).
     4.利用总线功能模型(BFM)思想,完成对MLB/AHB桥的RTL级仿真。
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  “rtl级”译为未确定词的双语例句
     In this paper,a reuse IP core design of UART_16C554 is described. With the architecture design,RTL-level design,functional simulation,and FPGA prototype verification,the UART_16C554 is a reuse IP core that fully compatible with de-facto 16C554.
     介绍了UART_16C554可复用IP核的设计,通过对器件进行结构划分,RTL级代码的设计,功能仿真,FPGA原型的验证,最终形成了一个与硬件16C554完全兼容的可复用IP核。
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     The estimated gates of our proposed architecture in SMIC 0.18 um technology are 15 500 and the estimated frequency of operation is 150 MHz.
     对该结构使用Verilog HDL语言进行RTL级描述,在SMIC 0.18 um工艺下综合得到最高工作频率为150 MHz,等效门数是15 500门。
     RISC Architecture Based Processor Design and RTL-Level Implementation
     基于RISC体系结构的处理器设计与RTL级实现
短句来源
     The estimated number of gates of the proposed architecture in SMIC 0.18 μm technology is 15 500,while the estimated frequency of operation is 150 MHz.
     对该结构使用Verilog HDL语言进行RTL级描述,在SMIC 0.18μm工艺下综合得到最高工作频率为150MHz,等效门数是15 500.
短句来源
     SystemC is a complete C++ based modeling platform,which supports designing the description at the register-transfer,behavioral and system level.
     SoC设计的复杂性对集成电路设计的各个层次,特别是对系统级芯片设计层次带来了新挑战. SystemC是一种完全基于C++的系统级建模语言,它同时支持RTL级、行为级和系统级描述.
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  rtl
Designs are usually given as Register-Transfer-Level (RTL) specifications, but most of today's hardware verification tools are based on bit-level methods.
      
These approaches are based on word-level descriptions as they are available on the RTL.
      
We introduce the main concepts of formal verification on the RTL and give a brief overview of existing techniques.
      
The use of retention time locking (RTL) in the development of unified procedures for the detection and quantitative determination of drugs in biological fluids was considered.
      
On applicability of the RTL prognostic algorithms and energy estimation to Sakhalin seismicity
      
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  rtl level
However, a purely Boolean representation is not expressive enough for many other real-world applications, including the verification of timed and hybrid systems, of proof obligations in software, and of circuit design at RTL level.
      
A behavioral level HDL model, and most RTL level models can be easily used over and over again on multiple designs.
      
At the RTL level of design the exact names of internal instance pins may not be known.
      
Based on the proposed architecture, the baseband-processor is described in Verilog HDL at RTL level.
      
Eventually, every system will be tested at both system-level and RTL level.
      
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In HDL synthesis systems of EDA design tools, it often needs to be judged in high-level synthesis, RTL-level synthesis and logic-level synthesis whether a logical function is a tautology. This paper gives a fast algorithm based on the concepts of cofactor, Shannon expansion and unate function to recursively and quickly judge if a given cube array of logical function is a tautology. This algorithm has been used in the VHDL synthesis system HLS/BIT.

在EDA设计工具的HDL综合系统中,高级综合、RTL级综合和逻辑级综合等都常常需要对逻辑函数进行永真式的判定。本文给出一种高效的永真式判定算法,该算法利用余因子、Shannon展开式和单边函数,对逻辑函数的多维体列阵进行快速有效的递归判定。该算法已经在自行研制的VHDL综合系统HLS/BIT中实际应用。

The methods to establish and simulate VHDL models of complex circuits are discussed in accordance with the instruction and system structure of neural processor slice. The slices algorithmic level and RTL level descriptions are given. The Two descriptions are simulated on the same test bench, verifying the correctness of both and equivalence of their functions. From this paper, we can see that the VHDLs powerful capacity of describing hardware will bring out constantly rising the level of circuit designs.

本文针对神经元计算芯片的指令系统和体系结构,详细讨论了复杂电路的VHDL建模及模拟验证方法,分别给出了该芯片的算法级描述和RTL级描述,并用相同的测试台对两级描述进行了模拟,验证了描述的正确性和功能的等价性.不难看出,VHDL语言描述硬件电路的强大能力为电路设计层次的不断提高创造了必要的条件

This paper discusses the design method of FPGA based on VHDL and expounds the basic concept of VHDL and the process of VHDL synthesis At last, it gives an example to illustrate how to compile the synthetic RTL VHDL code

本文详细讨论了用VHDL语言进行FPGA设计的方法,阐明了VHDL语言的基本概念以及VHDL的综合过程,并举例说明了如何编写可综合的RTL级VHDL代码。

 
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