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加法器电路
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  “加法器电路”译为未确定词的双语例句
     the other is the need to control the carrier powers so that they are same at the satellite input, however, they are adjusted by mechanical variable attenuator when it go beyond the modulator's adjustable range, but it will interrupt the communication signal while adjusting.
     针对上述不足,本文研制了卫星通信中频信号分配器,用单片机控制数控电调衰减器来调整载波电平,用微波放大器组成的加法器电路实现功率合成/分配,实现了设备各电路板的带电拔插,使该设备在解决了上述两点不足的情况下更适合卫星通信工程应用。
短句来源
     two new modified Domino adders are proposed;
     提出了两种改进型Domino加法器电路;
短句来源
     Meanwhile, there is the carry antecedence adder in the IC, IC is guaranteed to achieve the function of rapid counting.
     另外 ,在设计集成电路组件时 ,内部增设超前进位专用加法器电路 ,从而保证该组件经多级串联后整体电路仍能实现快速计数功能。
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     A new pulse stream digital/analogue based synapse multiplier/adder can be realized. The synapse weight values don't need learning, and it can also lessen the complexity of circuit.
     实现了一种脉冲流数字模拟混合突触乘法/加法器电路,而且该神经网络电路的突触权值不需要学习调整,降低了电路的复杂性。
短句来源
     A single-level perceptron network and field effect transistor circuit were used to make a digital/analogue-based synapse multiplier/ adder.
     利用单层感知器网络、场效应管电路实现了一种新的数字模拟混合突触乘法/加法器电路
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  相似匹配句对
     two new modified Domino adders are proposed;
     提出了两种改进型Domino加法器电路;
短句来源
     Basic Direct Current Circuits
     直流电路
短句来源
     Communication ICs
     通信电路
短句来源
     It is composed of directional coupler, controllable attenuator, delay line and adder.
     它由耦合器、衰减器、移相电路加法器组成。
短句来源
     Three-Operand Adder
     三操作数加法器
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  adder circuit
A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.
      
Proofs of properties of adder circuit descriptions are done by rewriting and induction.
      
Carry lookahead adder circuit is described using powerlists, a data structure introduced by Misra to support divide-and-conquer strategy used for designing data-parallel algorithms.
      
We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.
      
Based on a novel tunneldiode-transistor configuration a pulse former and a full adder circuit are being derived.
      
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Multiplier is the key in the Digital Signal Processing System. Pipelined Multiplier canachieve high speed with lower cost. In this paper, the structure of pipelined multiplier is given;two new modified Domino adders are proposed;the circuits are analysed and simulatedwith SPICE.The results show that the speed of the pipelined multiplier has been improvedsignificantly when the modified Domino adders are adopted.

乘法器是数字信号处理系统中的关键。流水线乘法器可以以较小的代价获得较高的平均速度。本文给出了流水线乘法器的结构;提出了两种改进型Domino加法器电路;对改进型电路作了分析和模拟。模拟结果表明,采用新的改进型Domino电路后,流水线乘法器的速度可以显著提高。

Current feedback amplifiers(CFA) have received attention in analog signal processing because they can provide not only constant bandwidths but also high slew rates. Several CFA based filters have been proposed and much work has been done by circuit transformation methods from opamp based circuits into CFA based circuits with higher performance. The purpose of this paper is to propose CFA based Kerwin Huelsan Newcomb(KHN)biquad from opamp based one. The opamp based KHN circuit is composed of two inverting...

Current feedback amplifiers(CFA) have received attention in analog signal processing because they can provide not only constant bandwidths but also high slew rates. Several CFA based filters have been proposed and much work has been done by circuit transformation methods from opamp based circuits into CFA based circuits with higher performance. The purpose of this paper is to propose CFA based Kerwin Huelsan Newcomb(KHN)biquad from opamp based one. The opamp based KHN circuit is composed of two inverting integrators and a three inputs summer. For proposing CFA based KHN circuit, the CFA based integrator in was used. The key work in the paper is to propose CFA based multi inputs summer suitable for KHN circuit. Two equivalent CFA based summers and two kinds of KHN circuits were proposed in the paper. As proposed CFA based KHN circuits are equivalent to the opamp based KHN circuit, they can perform the same functions. To verify the correction of the proposed circuit, a second order lowpass filter is designed and experimented. Commercial CFAs(AD844)were used in the experiment. The experimental results are in agreement with the theoretical results except the gain at resonant frequency, and they show the validity of the proposed circuits and the related method. As compared with Solimans circuit, the proposed circuits need only three active components(CFAs) each, it means two active components are saved, so the circuits are simpler than that in . Moreover, because two equivalent CFA based circuits can be generated from the opamp based KHN circuit, higher flexibility is achieved to optimize the circuit. So, the proposed circuits are simple, practical and versatile.

有源器件电流反馈放大器(CFA)由于能够提供常值带宽和高的电压摆率,因而在模拟信号处理电路中受到了广泛的重视并得到广泛应用.对两种用电流反馈放大器实现的加法器电路,进行了数学推证,并用这两种加法器和积分器实现基于CFA的Kerwin-Huelsman-Newcomb(KHN)电路,进行了设计和实验验证.实验结果与理论计算值吻合较好,充分证明了提出的加法器电路及所实现的基于CFA的KHN电路的正确性用CFA实现的KHN电路与Soliman用CCⅡ实现的KHN电路相比,少了两个有源器件,因而电路结构简单.而且,电路中只有同一种类型的有源器件,因而电路易于实现.同时,两种等效的加法器实现了两种形式的KHN电路,这就为电路的优选提供了可能性.另外,该电器还具有好的级联特性.因而,具有较高的实用价值

This paper uses the theory of a tail-difference for two random pulses, and presents a tail-difference algorithm for binary number. It ultimately solves counting error that pulses cross to produce. Meanwhile, there is the carry antecedence adder in the IC, IC is guaranteed to achieve the function of rapid counting. The experiment shows that design theory and properties fulfill needs of design. It fills the vacancy of IC two random pulses difference with the carry antecedence.

利用随机脉冲尾数求差原理 ,导出了二进制两路尾数求差的计算法。在不增加门速度的前提下 ,从根本上解决了随机脉冲因交叠所产生的计数错误。另外 ,在设计集成电路组件时 ,内部增设超前进位专用加法器电路 ,从而保证该组件经多级串联后整体电路仍能实现快速计数功能。集成电路运行实验表明 ,设计原理及运行性能完全满足设计要求 ,并可填补集成电路对随机脉冲求差的空缺。

 
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