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仿真与综合
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  simulation and synthesis
    The basic operation of the bus controller is described with the Altera's FLEX10K FPGA device and Verilog HDL, along with the function simulation and synthesis and the FPGA design of the PCI bus controller. This brings out the strong points of the FSM, such as its clear structure and easy maintance.
    同时结合AlteraFLEX10K的FPGA器件,采用Verilog硬件描述语言,描述该总线控制器的基本操作,并完成功能仿真与综合,实现了PCI总线控制器的FPGA设计,说明该有限状态机具有结构清晰、易于维护的特点.
短句来源
    This paper introduces a MIPS-based HDTV SoC platform and mainly deals with the design in the case of 5.1 channels of its audio PCM output module, and the function of the whole system is verified by simulation and synthesis.
    介绍了基于MIPS4KcTM内核的数字高清晰度电视(HDTV)SoC平台,主要针对5.1声道的情况提出了该平台上系统的音频PCM输出模块的设计方案。 并通过仿真与综合,验证了该模块能够达到系统总体设计的要求。
短句来源
  simulation and synthesis
    The basic operation of the bus controller is described with the Altera's FLEX10K FPGA device and Verilog HDL, along with the function simulation and synthesis and the FPGA design of the PCI bus controller. This brings out the strong points of the FSM, such as its clear structure and easy maintance.
    同时结合AlteraFLEX10K的FPGA器件,采用Verilog硬件描述语言,描述该总线控制器的基本操作,并完成功能仿真与综合,实现了PCI总线控制器的FPGA设计,说明该有限状态机具有结构清晰、易于维护的特点.
短句来源
    This paper introduces a MIPS-based HDTV SoC platform and mainly deals with the design in the case of 5.1 channels of its audio PCM output module, and the function of the whole system is verified by simulation and synthesis.
    介绍了基于MIPS4KcTM内核的数字高清晰度电视(HDTV)SoC平台,主要针对5.1声道的情况提出了该平台上系统的音频PCM输出模块的设计方案。 并通过仿真与综合,验证了该模块能够达到系统总体设计的要求。
短句来源
  “仿真与综合”译为未确定词的双语例句
    The Design Example of Verilog HDL and Its Simulation & Synthesis
    Verilog HDL设计实例及其仿真与综合
短句来源
    Dynamic simulation and comprehensive optimum design of working device of loader
    装载机工作装置的动力学仿真与综合优化设计
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    Marine Power Station Simulation and Integrated Management System
    船艇电站仿真与综合管理系统
短句来源
    Then the USB device controller was described by hardware description language. Afterthe design the modules were simulated, synthesized by ActiveHDL, Synplify and Maxplus II .
    以硬件描述语言对USB设备控制器进行了描述,并分别以ActiveHDL、Synplify和Maxplus Ⅱ完成了USB设备控制器的仿真与综合
短句来源
    This paper presents a new build-in self-test structure of SRAM based on LFSR and MARCHC+,which is designed for a 2K×8 embedded SRAM. The simulation waveform and synthesis results are provided as well.
    提出了一种基于LFSR与MARCH C+算法的SRAM内建自测试新结构,基于此结构设计了2k×8嵌入式静态存储器(SRAM)的内建自测电路,给出了电路的仿真与综合结果。
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  simulation and synthesis
Simulation and synthesis of elastic wave absorbers at the boundary of a rigid body: Incidence of longitudinal waves
      
This paper presents a methodology for hardware/software co-design with particular emphasis on the problems related to the concurrent simulation and synthesis of hardware and software parts of the overall system.
      
Elaborate simulation and synthesis tools at a higher design level aid the designer for a more controllable and maintainable product.
      
HDL design tools include at least HDL simulation and synthesis tools.
      
In Chapter 5, simulation and synthesis results of the LT coder have been presented.
      
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High privilege system call is the only way for low privilege procedure to obtain system service in protected mode. In order to prevent low privilege procedure from interfering with high privilege procedure, a call gate data structure is used to protect system call. Only if call gate checkup passes, control could transfer from low privilege level to high privilege level. After analyzing definition and data structures of system calls, an algorithm is given to implement them. A basic test unit called cell is extracted...

High privilege system call is the only way for low privilege procedure to obtain system service in protected mode. In order to prevent low privilege procedure from interfering with high privilege procedure, a call gate data structure is used to protect system call. Only if call gate checkup passes, control could transfer from low privilege level to high privilege level. After analyzing definition and data structures of system calls, an algorithm is given to implement them. A basic test unit called cell is extracted from the algorithm, it produces Boolean test value to control branch of the microprogram for system call. Cells are enumerated and extracted from system call algorithm to form a kind of cell group to establish Privileged system Call test Unit (PCU). Cell group solves a difficult problem in protected test unit design in protected microprocessor, and it has been used in the design of aviation embedded 16 bit microprocessor NCS. VHDL description at RTL level for PCU and the algorithm microprogram have been successfully synthesized and simulated with MENTOR GRAPHICS of EDA tools and its simulation proves the validity of PCU.

设计拥有我国自主版权的微处理器有着重大意义 .高特权级系统调用算法及高特权级系统调用测试单元PCU是拥有保护机制微处理器的重要组成部分 ,文中探讨了保护方式下高特权级系统调用的数据结构、定义 ,给出了高特权级系统调用算法 ,提出了高特权级系统调用测试单元 PCU的细胞群结构 ,并指出细胞是高特权级系统调用测试单元 PCU的基本测试单位 .细胞群结构概念的提出解决了微处理器保护测试单元结构设计的难题 ,使设计拥有自主版权的支持保护方式的微处理器成为可能 .细胞群结构已用于航空嵌入式拥有保护机制微处理器 NCS的设计 ,经 EDA工具 MENTOR GRAPHICS仿真与综合 ,验证了其正确性与有效性

A fast algorithm of extracting head contour is proposed for real-time image processing,which is accomplished by FPGA processor and host computer together.First,the segmentation threshold between background and head is computed by the host computer.Second,the head contour is detected in real time by FPGA processor.The advantages of the fast algorithm include easy computing,and fast implementation,etc.The algorithm reduces greatly data throughput of transmission and storing and alleviates the computational...

A fast algorithm of extracting head contour is proposed for real-time image processing,which is accomplished by FPGA processor and host computer together.First,the segmentation threshold between background and head is computed by the host computer.Second,the head contour is detected in real time by FPGA processor.The advantages of the fast algorithm include easy computing,and fast implementation,etc.The algorithm reduces greatly data throughput of transmission and storing and alleviates the computational load of host computer.The devices are low cost by cutting off the expensive image capture and compression card and the high-speed hard disk.The FPGA processor is designed as pipelined architecture.The average time of processing every pixel in each step is less than70ns.The results of emulation and synthesis show that extracting head contour from a frame of standard PAL video image is completed within40ms.

为解决三维扫描仪的实时性,文章提出了以FPGA处理器与PC主机交互式共同完成提取轮廓线的快速算法。该算法由两个阶段组成:第一阶段由主机计算背景与目标的分割阈值。第二阶段由FPGA处理器实时检测轮廓线位置信息。该快速算法具有计算简单、实现速度快等优点,并且减少了传输与存储的数据量,减轻了后面主机计算工作量。同时,省掉了昂贵的图像采集压缩卡与高速硬盘,降低了成本。可重构FPGA处理器设计成流水线结构,对每个像素的平均处理时间控制在70ns以内。仿真与综合结果表明:从一帧720576标准PAL制视频图像中提取轮廓线信息可在40ms内实时完成。

The CORDIC (COordinate Rotation DIgital Computer) algorithm is described, and a method for implementing a numerically controlled oscillator (NCO) based on this algorithm is presented in the paper Results from simulation and synthesis indicate that the implementation has the advantages of high precision, low error and simple structure As compared with the NCO based on lookup table, it is easier for implementation in ASIC

 提出了一种基于CORDIC(COordinateRotationDIgitalComputer)算法的流水线型数控振荡器的实现方法。硬件描述语言的仿真与综合结果表明,采用这种方法设计的数控振荡器精度高、误差小、结构简单;与基于查找表的数控振荡器相比,更易于ASIC实现。

 
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