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均方差抖动
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  rms jitter
     Its rms jitter is 9 ps and current dissipated is 3.9 mA.
     均方差抖动 9ps,核心部分电源电流消耗 3.9m A。
短句来源
     Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.
     双模预分频实现了高速低抖动低功耗,双模预分频器工作在除8状态输出133MHz频率时,均方差抖动小于2ps;
短句来源
     An RMS jitter of 2ps is measured on the output signal at 118.3MHz. It is less than 0.02% of the clock period.
     均方差抖动在输出周期为118·3MHz时仅为2ps,约占输出周期的0·02%.
短句来源
  相似匹配句对
     All data weve done analysis of variance.
     所有数据进行方差分析。
短句来源
     Its rms jitter is 9 ps and current dissipated is 3.9 mA.
     方差抖动 9ps,核心部分电源电流消耗 3.9m A。
短句来源
     Accurate Design of Mean-Square Deviation of Raw Silk in Multi-End Reeling
     正确设计立缫生丝方差
短句来源
     should be the new synonym of it.
     为其异名。
短句来源
     All the 5 eases showed (?) ≥(?)
     ≥(?)
短句来源
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  rms jitter
The CDR exhibits an RMS jitter of ± 1.2?ps and a peak-to-peak jitter of 5?ps.
      
The RMS jitter can then be derived from the probabilities and the delay values.
      
An on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper.
      
Achieving this theoretical condition in the presence of a jittered system would necessitate an RMS jitter of less than 2ns.
      
An increase in RMS jitter by 25% and 10% decrease in oscillation frequency of VCO can be observed after 4 hours hot carrier stress.
      
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Two key building blocks of high-speed frequency synthesizer in RF front-end of 802.11a are presented. One is -G_mLC-based oscillator and the other high-speed dual-modulus prescaler. Both blocks are implemented in a 0.18 μm standard CMOS process, and reach maximum center frequency of 4.5 GHz using a 1.8 V power supply, while maintaining reasonable phase noise (-119 dBc/Hz @ 500 kHz offset) and offering a wide tuning range of 15%. Dual-modulus prescaler can work well on high speed with lower jitter and lower power...

Two key building blocks of high-speed frequency synthesizer in RF front-end of 802.11a are presented. One is -G_mLC-based oscillator and the other high-speed dual-modulus prescaler. Both blocks are implemented in a 0.18 μm standard CMOS process, and reach maximum center frequency of 4.5 GHz using a 1.8 V power supply, while maintaining reasonable phase noise (-119 dBc/Hz @ 500 kHz offset) and offering a wide tuning range of 15%. Dual-modulus prescaler can work well on high speed with lower jitter and lower power dissipation. Its rms jitter is 9 ps and current dissipated is 3.9 mA.

论述了一种应用于 80 2 .1 1 a无线局域网射频前端高速频率合成器中两个关键模块的设计 :负阻 LC压控振荡器 ( VCO)与高速双模分频器 ( DMP)的射频全芯片集成。采用 0 .1 8μm CMOS工艺 ,1 .8V电压下进行仿真 ,VCO仿真偏离 4.5 GHz中心频率 5 0 0 k Hz时 ,相位噪声为 - 1 1 9d Bc/Hz,VCO调谐范围为1 5 %。除 8/9双模预分频器实现了高速、低抖动、低功耗设计。均方差抖动 9ps,核心部分电源电流消耗 3.9m A。

An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of...

An optimized method is presented to design the down scalers in a GHz frequency synthesizer.The down scalers are comprised of dual modulus prescaler (DMP) and programmable & pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively.Using a DMP high speed,lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps.The flexibility and reusability of the programmable divider is high;its use could be extended to many complicated frequency synthesizers.By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

介绍了一种应用于GHz级高速频率合成器的数模混合下变频模块.采用了高速射频双模预分频器与数字逻辑综合生成的可编程吞脉冲分频器相结合的设计方法.双模预分频实现了高速低抖动低功耗,双模预分频器工作在除8状态输出133MHz频率时,均方差抖动小于2ps;可编程吞脉冲分频器算法灵活、设计复用性强,该算法可以灵活运用到许多复杂频率综合系统.相比较而言,该设计获得了更好的高频电路性能与设计复用性.

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency (RF) front-end is presented,and design of a voltage controlled oscillator (VCO) and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS (complementary metal-oxide-semiconductor transistor) process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel...

A scheme of a frequency-hopping frequency-synthesizer applied to a Bluetooth ratio frequency (RF) front-end is presented,and design of a voltage controlled oscillator (VCO) and dual-modulus prescaler are focused on.It is fabricated in a 0.18 μm mixed-signal CMOS (complementary metal-oxide-semiconductor transistor) process.The power dissipation of VCO is low and a stable performance is gained.The measured phase noise of VCO at 2.4GHz is less than -114.32 dBc/Hz.The structure of the DMP is optimized and a novel D-latch integrated with “OR” logic gate is used.The measured results show that the chip can work well under a 1.8 V power supply.The power dissipation of the core part in a dual modulus prescaler is only 5.76mW.An RMS jitter of 2ps is measured on the output signal at 118.3MHz.It is less than 0.02% of the clock period.

提出了应用于蓝牙射频前端的跳频频率综合器的设计方案,并介绍了关键模块压控振荡器与双模预分频器的设计技术,采用混合0·18μmCMOS工艺进行了流片验证.设计的压控振荡器性能稳定,低功耗低相噪,频率在2·4GHz时测试相位噪声达-114·32dBc/Hz@2·4MHz.对双模分频器进行了设计优化,并采用一种集成“或”逻辑的锁存器结构,降低了功耗,提高了电路速度.测试结果显示电路在1·8V时稳定工作双模分频器核心功耗仅5·76mW;均方差抖动在输出周期为118·3MHz时仅为2ps,约占输出周期的0·02%.

 
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