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时延驱动
相关语句
  timing driven
     Timing Driven Steiner Tree Algorithm Based on Sakurai Model
     基于Sakurai模型的时延驱动Steiner树算法
短句来源
     Timing driven layout system for gate array and standard cell design——Tiger
     时延驱动的门阵和标准单元布图系统——Tiger
短句来源
     Application of Self Organizing Neural Network in Timing Driven System Partitioning on MCM
     自组织神经网络在时延驱动的MCM系统划分中的应用
短句来源
     A Method of VLSI Timing Driven Placement
     一种时延驱动的VLSI布局方法
短句来源
     Neural Network Based Timing Driven Floorplanning
     基于神经网络的时延驱动版图规划算法
短句来源
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  timing-driven
     The BSG-Based Timing-driven Placement
     基于BSG的时延驱动布局
短句来源
     Timing-driven (or performance-driven) BBL placement based on BSG (bounded slicing grid) structure is studied and implemented. This is a Non-slicing path-oriented time-delay optimizing BBL algorithm . It is straightforward and easy to be implemented.
     本文采用BSG (bounded slicing grid) 结构对时延驱动 (timing driven) 或称为性能驱动 (performance driven)布局问题进行了研究和实现,此算法是一种Non-slicing的面向路径的时延优化BBL (Building Block Layout),算法思路简洁,易于实现,实验效果令人满意。
短句来源
     The work of present timing-driven routing algorithms mainly is partitioned into three aspects:the delay model,the objective formulation and the solution space.
     现有时延驱动布线算法的工作主要分为三个方面:时延模型、目标形式化、解空间。
短句来源
     A Timing-driven Standard-cell Placement Algorithm Based on Deterministic Simulated Annealing
     一个基于确定性退火的时延驱动标准单元布局算法
短句来源
     Based on the sequence of the development of delay model,this paper introduces timing-driven routing algorithms presented in the decade.
     论文以时延模型为主线,介绍了近10年来提出的时延驱动的布线算法。
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  “时延驱动”译为未确定词的双语例句
     VLSI timing dviven layont and power and Groand Nets routing
     VLSI时延驱动布局和电源网布线研究
短句来源
     Hierarchical Timing-Driven Initial Placement for Row-Based ICs
     分级的时延驱动布局算法
短句来源
     Timing-Driven Entire Spacing Global Routing
     时延驱动的整平面整体布线算法
短句来源
     APPLICATION OF SELF-ORGANIZING NEURAL NETWORK IN TIMING-DRIVEN PLACEMENT
     Kohonen神经网络在时延驱动布局中的应用
短句来源
     A Crosstalk and Delay Driven Global Routing Algorithm
     一种串扰和时延驱动的总体布线算法
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  timing driven
Detailed module by module timing scripts help efficient Placement and Routing for Timing Driven Layout and help meet timing.
      
For the Virtex-5 architecture, timing driven packing and placement is the only way to run MAP.
      
More precisely, the regression analysis permits us to determine the existence of market timing driven by constitution and rebalancing rules.
      
No clock-tree is required, routing does not need to be timing driven, and there are no clock-related timing violations.
      
This ongoing project currently addresses the timing driven placement and global routing of fixed-die standard cell blocks.
      
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  timing-driven
First, the timing-driven placement algorithm is used to find the global optimal solution.
      
The results show that the maximum delay can decrease by 30% in our timing-driven placement and in the second step the maximum congestion will decrease by 10% while the timing behavior is unchanged.
      
Timing-driven MultiChip Module routing algorithm with crosstalk consideration
      
This paper presents a timing-driven MultiChip Module (MCM) routing algorithm considering crosstalk, which maximizes routing density while minimizing vias and total wire length.
      
Above this platform a fixed die standard cell timing-driven placement and global routing flow has been developed.
      
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Timing performance is important to high performance VLSI. This paper pre sents a new method of timing driven placement. In initial placement we propose a new way giving weights to the nets, and in iterative placement, we present a concept called Equal Position Field. The experiment results show that this is an efficient method of timing driven placement.

时廷特性对于高性能的超大规模集成电路(VLSI)来讲是十分重要的。本文提出了一个新的时延驱动的布局方法。在初始布局中,我们提出了给线网加权的新方法,在迭代改善布局中提出了等位场的概念。实验结果表明:这是一种有效的时延驱动布局方法。

A building-block layout system for large scale ASIC chip design is presented in this paper. A few advanced placement and routing algorithms of the world are adopted and some new techniques for layout optimization such as timing-driven placement, planar routing for P/G nets, optimal channel definition and ordering, dynamic module shifting and optimization of detailed routing are herewith introduced. The staisfactory results gaining from the experiments have ensured the good performance of the system.

本文介绍一个基于积木块方式的大规模专用集成电路芯片版图设计系统。该系统不仅采用了近期国际上先进的布局布线算法,而且引入了时延驱动布局、电源网平面化布线、通道最优划分和排序、单元动态调整以及详细布线优化等新的布图优化技术。

In this paper,we present the idea of timing driven floorplanning.While optimizing the interconnection delay between cells using improved GFDR,We use nonlinear programming method to reduce the cell delays and interconnection delays in critical paths.The result shows that it is an effective method for optimizing layout delay of VLSI.

本文提出了时延驱动布图规划(TimingDrivenFloorplanning)的思想。在用改进的广义力矢量法优化功能单元间连线时延的同时,运用非线性规划的方法进一步优化关键路径上功能单元的时延及连线时延,结果表明,这是一种有效的优化版图时延的方法。

 
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