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rtl描述
相关语句
  rtl description
     A RTL DESCRIPTION FOR THE FINITE AUTOMATON M
     有限自动机M的RTL描述
短句来源
     On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
     文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
     On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
     在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
     If there is such a tool, for the control logic designed in Stateflow, the system engineer could provide the RTL description of the system to the IC engineer. Thus, the work of programming in HDL will be omitted, and the IC engineer could have more time to the design coming-up.
     如果存在这样的转换工具,对于使用Stateflow设计的控制逻辑部分,系统工程师可以直接向IC工程师提供系统的RTL描述,省去了IC工程师在硬件描述语言上的编程工作,使得他能够将更多的精力放在后续的设计中。
短句来源
     By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.
     提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 . 此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径
短句来源
  rtl
     On the basis ofthe analysis of features of Verilog HDL and RTL description, this paper shows themethod of the construction of the module library and the conversion from RTL HDLdescription to gate-level description.
     文中分析了Verilog HDL语言和RTL描述的特点,介绍了该编译器解析Verilog HDL描述、创建功能模块类库以及将Verilog HDL的RTL描述转化为无层次分块的门级描述的基本原理和主要问题的解决策略。
短句来源
     On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.
     在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。
短句来源
     A RTL DESCRIPTION FOR THE FINITE AUTOMATON M
     有限自动机M的RTL描述
短句来源
     As usually using HDL to describe hardware in RTL level and using C or C++ programming language to describe software,it brings the difficulty of Co-verification and Co-simulation so as to leading the repeating of design process in traditional HW/SW Co-design.
     在传统的软硬件协同设计中,硬件采用的是RTL描述(用硬件描述语言HDL描述),而软件通常采用C或者C++语言进行描述,这种语言描述的不一致会加大协同验证仿真的难度,从而导致系统设计过程的反复。
短句来源
     As usually using HDL to descript hardware in RTL level and using C or C++ programming language to descript software, it brings the difficulty of coverification and cosimulation so as to lead the repeating of design process in traditional HW/SW codesign.
     在传统的软硬件协同设计中,硬件采用的是RTL描述(用硬件设计语言HDL描述),而软件通常采用C或者C++语言进行描述,这种语言描述的不一致会加大协同验证仿真的难度,从而导致系统设计过程的反复。
短句来源
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  “rtl描述”译为未确定词的双语例句
     This IP Core is described by Verilog HDL, synthesized based on SMIC 0.35um technology library.
     设计的RTL描述语言使用的是Verilog HDL语言。 工艺库使用的是SMIC 0.35um工艺库。
短句来源
     In order to extract the control constraints, an instr-state-ctrlsig table is created to store the control signal name whose value is high for every state of each instruction.
     为了提取控制约束,根据PUT的RTL描述创建一个instr-state-ctrlsig表,来记录每条指令的每个状态下值为高的那些控制信号名。
短句来源
     Control and data constraints are extracted from the RT-level description of PUT and constraint ATPG is excuted at gate level.
     从PUT的RTL描述里提取出控制约束和数据约束,并结合这些约束在门级进行有约束的测试产生。
短句来源
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  rtl description
Verisym symbolically simulates the execution of a circuit, given as either a transistor-level schematic or an RTL description, to check a property, given as the stimulus to the circuit and the expected response.
      
The need to inject faults on implicit variables of the RTL description is analyzed.
      
Column six shows the number of transitions when the scan chain is partitioned as mentioned in the RTL description.
      
Even though both methodologies generate RTL description, these di er in many aspects.
      
From these operations, bit-true cycle-accurate simulators and a synthesizable RTL description are automatically generated.
      
更多          
  rtl
Designs are usually given as Register-Transfer-Level (RTL) specifications, but most of today's hardware verification tools are based on bit-level methods.
      
These approaches are based on word-level descriptions as they are available on the RTL.
      
We introduce the main concepts of formal verification on the RTL and give a brief overview of existing techniques.
      
The use of retention time locking (RTL) in the development of unified procedures for the detection and quantitative determination of drugs in biological fluids was considered.
      
On applicability of the RTL prognostic algorithms and energy estimation to Sakhalin seismicity
      
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This paper introduces the characterlistics of VHSIC hardware description language. The difference between VHDL and computer advanced language, as well as the limitations of register RTL are discussed, and the methods of reducing the occupying rate of the hardware resource in design of programmable application specific integrated circuit are presented.

介绍了硬件描述语言 VHDL的特点 ,讨论了 VHDL语言与计算机高级语言的区别及寄存器 RTL描述方式的限制 ,阐述了在可编程 ASIC设计中降低目标器件硬件资源占用率的技巧及方法

Discusses the feasibility of reusing the controller synthesis technology in high level synthesis in the RTL synthesis, and puts forward a method to implement RTL synthesis. By dividing RTL description into combinational logic and sequential logic, the method reuses the combinational logic synthesis and sequential logic synthesis in the controller synthesis, thus reducing the time used in developing RTL synthesis.

讨论在 RTL综合中重用高级综合中控制器综合技术的可行性 .提出一种通过将RTL描述划分为时序逻辑与组合逻辑后 ,重用控制器综合中的组合逻辑综合和时序逻辑综合实现 RTL综合的方法 .此方法有效地利用了已有的成熟技术 ,为缩短 RTL综合的开发时间提供了一种有效途径

A Verilog HDL compiler for ISCAS85/89 Benchmarks as a utility for the study of RTL combinational circuits is introduced.On the basis of the analysis of features of Verilog HDL and RTL description,methods of the construction of the module library and the conversion from RTL HDL description to gate level description are showed.

设计了一个针对 ISCAS 85/89Benchmark,用于 RTL组合电路 Verilog HDL描述的编译器。这个编译器可以作为 RTL电路测试研究的辅助工具。在对 Verilog HDL和 RTL描述的特点进行分析的基础上 ,阐述了该编译器解析 Verilog HDL描述、创建功能模块类库和将 RTL描述转化为无层次分块的门级描述的基本原理 ,提出了主要问题的解决策略。

 
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