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algorithm
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  算法
    Research of Parallel ATPG Algorithm and Prototype System Design
    并行ATPG算法理论与原型系统设计技术研究
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    Studies on the Convergence Performance of Least Mean Square (LMS) Algorithm and Its Applications
    LMS算法收敛性能研究及应用
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    Research on High-level Synthesis Algorithm and the Comparison of Two Sequential Synthesis Theories in EDA
    EDA中高层次综合算法及两种时序综合理论比较研究
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    Study on Algorithm and VLSI Implementation of High-Speed QAM Demodulator
    高速QAM解调器的算法及VLSI实现研究
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    Algorithm of Electrical Impedance Tomography and Experiment Research Based on Fast Newton's One-Step Error Reconstructor
    基于快速牛顿一步误差重构的电阻抗成像算法和实验研究
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  “algorithm”译为未确定词的双语例句
    Study on Adaptive Nonuniformity Correction Algorithm for IRFPA Based on Imaging Guidance Condition
    基于成像制导状态的自适应IRFPA非均匀性校正技术研究
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    A Channel Layout Algorithm and the Study of a Mask Artwork Design System for SC Circuits
    一种通道式布图算法及SC电路版图设计系统的研究
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    CENTROID ALGORITHM IN PIXEL CCD SUN SENSOR
    CCD太阳角计中的形心计算法
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    A New Algorithm for Analysis of Nonlinear Oscillator with Many Nonlinear Elements Using Volterra Series
    一种用Volterra级数分析含多个非线性元件振荡电路的新方法
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    Synthesis of Binary Computer-Generated Hologram by Optimal Recursive Direct Binary Search Algorithm
    Synthesis of Binary Computer-Generated Hologram by Optimal Recursive Direct Binary Search Algorithm
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  algorithm
This paper gives an algorithm for computing invariant rings of reductive groups in arbitrary characteristic.
      
The algorithm presented here computes a geometric characteristic of this action in the case where G is connected and reductive, and $\rho$ is a morphism of algebraic groups: The algorithm takes as input the
      
We present an algorithm for computing the invariant field k(X)G.
      
More precisely, we give an algorithm for computing a nonempty open subset of X with a geometric quotient.
      
We show that the rate of convergence for this reconstruction algorithm is geometric and computable in advance.
      
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This paper introduces low noise circuit design formulae for different stages of correlating preamplifier and principle of low noise eleotronic design derived from the input equivalent algorithm of noise source and E_n-I_n model of noise parts. It also analyses the noise properties of various precircuits (include feedback network).

本文中作者采用了噪声源的输入端等值计算法及噪声器件的E_n-I_n模型推导了有关前置放大器的各级低噪声电路设计公式及低噪声电子设计原则.分析了各种常用前置电路(包括反馈网络)的噪声性能。

It is proposed that the Karnaugh maps be constructed and squares be grouped by the image method in order to study the digital logic functions and an algorithm is derived. The image Karnaugh map is seen to be more strict and is applicable to any complicated cases in principle. The original Karnaugh map is simply a special case of the image one given here.

本文针对卡诺图的缺陷,提出采用镜像法进行构图和组群来研究数字逻辑函数,导出了其算法规则.这种镜像卡诺图,算法严格,原则上能适应于任何复杂情况,卡诺图只是镜像卡诺图的一种特殊情况.

In this paper the constrution method and function of the multi-input paralleladdition network with the ROM table look-up method are presented.First,a counter-ROM without carry,and with capability of direct processing two's complement isintroduced.Then,the Multi-input parallel addition network construction algorithm basedon counter-ROMs is presented.Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.The Multi-input pa allel addition network proposed here...

In this paper the constrution method and function of the multi-input paralleladdition network with the ROM table look-up method are presented.First,a counter-ROM without carry,and with capability of direct processing two's complement isintroduced.Then,the Multi-input parallel addition network construction algorithm basedon counter-ROMs is presented.Finally,the decisive factor of the number of ROMsand the stages of the addition network are discussed.The Multi-input pa allel addition network proposed here has a very flexiblehardware configlaration and offers an extremely high throughput rate.

随着集成电路的飞跃发展,有可能用记忆元件来实现运算电路。本文提出,用ROM(Read—Only Memory)做为运算单元的多输入并行加法网络的构成方法。首先,提出能够处理补码的并行计数器ROM。其次,提出用计数器ROM 作为基本组成单元的多输入并行加法网络的构成算法。最后,推导求出多输入并行加法网络所需的ROM 数的公式,并对影响速度的级数进行讨论。本文提出的多输入并行加法网络有对于任何加权(Weight)的输入都可以进行高速处理的特长。因此,这种电路很适合于高速乘一加运算电路和卷积运算电路,以及高速数字滤波器电路。

 
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