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   vlsi implementation 的翻译结果: 查询用时:0.214秒
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vlsi implementation     
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  vlsi实现
     Design of I~2C slave device structure and Its VLSI implementation
     I~2C Slave器件内部结构设计及VLSI实现
短句来源
     Algorithm and VLSI Implementation of AES S-Box
     AES加密算法中S-BOX的算法与VLSI实现
短句来源
     VLSI Implementation of EBCOT Decoder in JPEG2000 System
     JPEG2000中EBCOT解码器的VLSI实现
短句来源
     VLSI Implementation of H.264 Video Encoder
     H.264视频编码器的VLSI实现
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     Study on Algorithm and VLSI Implementation of High-Speed QAM Demodulator
     高速QAM解调器的算法及VLSI实现研究
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  硬件实现
     A Motion Adaptive3D De-interlacing Algorithm and Its VLSI Implementation
     一种运动自适应3D去隔行算法及其硬件实现
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     Thirdly, according to the characteristics of H.264/AVC, a motion estimation fastalgorithm based on hardware------Extended Three-Step Search algorithm is proposed. the VLSI implementation complexity of motion estimation in video encoding is analyzed.
     第三,根据H. 264/AVC的特点,提出了一种基于VLSI的快速搜索算法——扩展三步搜索算法,该算法在搜索窗内搜索点数和搜索步数固定,搜索点排列整齐而有规律,算法复杂度低,易于硬件实现,然后作了分析和软件测试,给出了算法的硬件结构。
短句来源
     An Improvement in the VLSI Implementation of Montgomery Algorithm
     一种Montgomery模乘算法硬件实现的改进电路
短句来源
     Lastly, the thesis investigate the application of log-domain filter in the hard-disk-drive (HDD) read channels, audio-frequency filtering, the design of current-mode phase-locked loop ( PLL) and the VLSI implementation of wavlet transformation etc, then introduces the square-root domain filters using quadratic law of MOSFET in strong inversion region which also belong to the class of companding filters, a square-root domain integrator is also presented.
     最后本文考察了对数域滤波器(电路)在音频滤波、硬盘驱动器读取通道、小波变换VLSI硬件实现等方面的应用,并阐述了与对数域压扩滤波类似的基于强反型MOSFET实现的平方根域压扩滤波的基本原理及设计方法,给出了基本的平方根压扩积分器的设计实现并介绍了平方根压扩滤波电路的研究及应用现状,以期完善压扩滤波的概念。
短句来源
     Experimental results demonstrate that this algorithm has similar performance to that of the full search algorithm,and owing to its inherent parallelism and low complexity it is suitable for VLSI implementation.
     由于其具有低复杂度和进化算法的内在并行性的特点,故该算法适合硬件实现
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  vlsi设计
     The Algorithm Study on CABAC Based on H.264/AVC and Its VLSI Implementation
     基于H.264/AVC 中CABAC算法研究及VLSI设计
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     The Algorithm Study on CAVLC Based on H.264/AVC and Its VLSI Implementation
     基于H.264/AVC中CAVLC算法研究及VLSI设计
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     A Study on Transform and Quantization Based on H.264/AVC and Its VLSI Implementation
     基于H.264/AVC中整数变换与量化的研究及VLSI设计
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     VLSI implementation of RSA cryptosystem based on the Booth-encoded montgomery module
     基于Booth编码模乘模块RSA的VLSI设计
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     A Low-power VLSI Implementation of a Motion Estimation Block in MPEG-4
     MPEG-4中运动估值的低功耗VLSI设计
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更多       
  vlsi硬件实现
     Lastly, the thesis investigate the application of log-domain filter in the hard-disk-drive (HDD) read channels, audio-frequency filtering, the design of current-mode phase-locked loop ( PLL) and the VLSI implementation of wavlet transformation etc, then introduces the square-root domain filters using quadratic law of MOSFET in strong inversion region which also belong to the class of companding filters, a square-root domain integrator is also presented.
     最后本文考察了对数域滤波器(电路)在音频滤波、硬盘驱动器读取通道、小波变换VLSI硬件实现等方面的应用,并阐述了与对数域压扩滤波类似的基于强反型MOSFET实现的平方根域压扩滤波的基本原理及设计方法,给出了基本的平方根压扩积分器的设计实现并介绍了平方根压扩滤波电路的研究及应用现状,以期完善压扩滤波的概念。
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      vlsi implementation
    Then, under the same cost (= time × the number of processors =O(n2)), we provide a partitionable strategy when the RM doesn't offer sufficient processors; this overcomes the hardware limitation and is very suitable for VLSI implementation.
          
    In this paper, we address the issues of designing lowpower VLSI implementation of the Code DivisionMultiple Access (CDMA) receiver.
          
    The implementation methodology presented here leads to a VLSI implementation structure.
          
    A VLSI implementation is also highly suitable for the intrinsic parallel nature of neural networks.
          
    The LDPC codes are developed in tandem with the underlying VLSI implementation technique, without compromising chip design constraints.
          
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    The growing complexity of avionics systems has led it to distributed processing. This paper introduces an 1553B based on Experimental Prototype of Distributed Avionics System(EPDAS) , and discusses its related components of the information transfer mechanism, such as the protocol of the bus communication, the communication program and the Bus Interface Unit(BIU) .After having analyzed the shortcoming of the conventional Synchronous Bus Control strategy, this paper presents a bus control strategy of PCCR (Polling...

    The growing complexity of avionics systems has led it to distributed processing. This paper introduces an 1553B based on Experimental Prototype of Distributed Avionics System(EPDAS) , and discusses its related components of the information transfer mechanism, such as the protocol of the bus communication, the communication program and the Bus Interface Unit(BIU) .After having analyzed the shortcoming of the conventional Synchronous Bus Control strategy, this paper presents a bus control strategy of PCCR (Polling Combined with Command/Respones) , which can raise the efficiency of bus data transfer.The adoption of pipeline processing in the BIU design for the EPDAS system makes the BIU not only faster but also simplified so as to be suitable for VLSI implementation.The concept of Pseudo-DMA Control, proposed in the paper, further simplifies the hardware of the BIU. The efficient interconnection via shared memory between the BIU and its host computer is easy to control and implement.

    航空电子系统日益增长的复杂性使其必须走向分布式处理的道路。本文介绍一个基于1553B总线的分布式航空电子系统的实验模型——EPDAS系统,讨论了EPDAS系统信息传输机构的有关组成部分:总线通信协议、通信管理软件和总线接口,本文在分析传统的同步总线控制方式的缺点之后,提出了询问和命令/响应相结合的总线控制方式,该方式能提高总线传输的效率和实时性。在EPDAS系统的总线接口设计中,引入了流水线并行处理技术,解决了总线接口的瓶颈问题,并使之易于VLSI化;伪DMA控制的概念,使总线接口电路更加简化;共享存贮器的互连技术,具有效率高、控制简单、容易实现等优点。EPDAS系统结构合理、效率高,符合国情、适合于新一代的飞机。

    Based on the 32 kbit/s ADPCM-algorithm suggested by the CCITT Recommendation G.721, in the DSP implementation of PCM/ADPCM transcoder we use six-order fixed poles instead of the two adaptive-poles, which are recommended by CCITT. This method can decrease the operation time and reduce the number of DSP (TMS 32010) to a half. At the same time the performance of our algorithm satisfies the standard of CCITT recommendation G721. This paper also proposes a method of implementation of 60 PCM/ ADPCM transcoder,...

    Based on the 32 kbit/s ADPCM-algorithm suggested by the CCITT Recommendation G.721, in the DSP implementation of PCM/ADPCM transcoder we use six-order fixed poles instead of the two adaptive-poles, which are recommended by CCITT. This method can decrease the operation time and reduce the number of DSP (TMS 32010) to a half. At the same time the performance of our algorithm satisfies the standard of CCITT recommendation G721. This paper also proposes a method of implementation of 60 PCM/ ADPCM transcoder, which is based on pipeline processing. Even though complicated, the method is suitable for VLSI implementation, which has smaller volume, lower-power consume and lower-price than the DSP implementation.

    根据CCITT G.721建议32 kbit/s ADPCM算法,本文在用DSP实现PCM/ADPCM转换器场合,用六阶固定极点代替CCITT建议的二阶自适应极点,缩短运算时间,该传输性能仍达到了CCITT规定指标,使转换器需用TMS 32010数目减半。本文还提出一种60路PCM/ADPCM转换器并行处理流水作业实现方案。虽实现复杂,但便于VLSI集成,其体积、功耗、成本较DSP小得多。

    A novel systolic array architccture for computing discrete orthogonal transforms such as DCT, DHT(DWT) and DFT is proposed. The systolic algorithm is based on FFCT proposed by Vetterli-Nussbaumer and the recursive equation of trigonometric functions. In this paper, we preset the processing elements based on a special butterfly computation and discrible the systolic array implementations for computing DCT, DHT(DWT) and DFT respectively. By use of the main feature of the two systolic array for DCT, a full 2-D...

    A novel systolic array architccture for computing discrete orthogonal transforms such as DCT, DHT(DWT) and DFT is proposed. The systolic algorithm is based on FFCT proposed by Vetterli-Nussbaumer and the recursive equation of trigonometric functions. In this paper, we preset the processing elements based on a special butterfly computation and discrible the systolic array implementations for computing DCT, DHT(DWT) and DFT respectively. By use of the main feature of the two systolic array for DCT, a full 2-D DCT array is presented. All these computations can be fulifiled in real domain. It is argued that because ofhigh degree Of simplicity, regularity, suitability and concurrency inherent to these designs, their VLSI implementation will be cost effective.

    本文提出一种新型计算离散正交变换如DCT、DHT(DWT)和DFT的脉动阵列实现.脉动算法是基于Vetterli-Nussbaumer提出的FFCT和三角函数递归公式.文中绐出了两种基于特殊蝶形运算的处理单元和两种计算DCT,DHT(DWT)和DFT的脉动阵列实现.利用两种不同的DCT脉动阵列的特点,文中也给出了二维DCT脉动阵列实现,所有运算都在实数域中进行.由于这些计算具有高度的简便性、规则性、灵活性和一致性,它们的超大规模集成实现将是有效的.

     
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