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decoder     
相关语句
  解码器
     Research on High Speed Video Decoder Design
     高速视频解码器设计研究
短句来源
     Motion Estimation, Transform and Decoder Optimization in H.264/AVC
     H.264/AVC中运动估计、变换与解码器优化
短句来源
     Research and Implementation of Digital Television Source Decoder Based on Generic DSP
     基于通用DSP的数字电视信源解码器的研究与实现
短句来源
     MP3 Decoder IP Design and Reusability Research
     MP3解码器IP设计及重用性研究
短句来源
     Low Power MP3 Decoder and Its Design-for-Testability Techniques
     低功耗MP3解码器设计及其可测性分析
短句来源
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  译码器
     VLSI implementation for 2.5Gb/s Reed-Solomon decoder
     2.5Gb/s Reed-Solomon译码器的VLSI优化实现
短句来源
     Design and FPGA Implementation of RS(255,223) Decoder
     RS(255,223)译码器的设计与FPGA实现
短句来源
     Design of the RS(255,223) Decoder Based on FPGA
     基于FPGA的RS(255,223)译码器的设计
短句来源
     Design of the decoder of BCH(31,21) code based on FPGA
     基于FPGA的BCH(31,21)码译码器的设计
短句来源
     Implementation of 47Mb/s RS Decoder
     47Mb/s RS码译码器的实现
短句来源
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  解码
     VS1001K: Feature and Application of MP3 Decoder
     MP3解码芯片VS1001K特点及应用
短句来源
     H.264 Decoder Optimization for Trimedia DSP
     基于Trimedia DSP的H.264解码算法优化
短句来源
     Implementation and Optimization of H.264 Decoder Based on ADDSP-BF533
     H·264解码在ADDSP-BF533上的实现和优化
短句来源
     8B/10B encoder and decoder design
     8B/10B编解码的IP核设计
短句来源
     CPLD Implementation of 8B/10B Encoder/Decoder for Gigabit Ethernet
     千兆以太网中的8B/10B编解码的CPLD实现技术
短句来源
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  译码
     Realization of H.263 coder/decoder system using TMS320C6201
     用TMS320C6201实现H.263编译码系统
短句来源
     Application of RS Encoder or Decoder Based on FPGA APEX20K
     基于FPGA APEX20K实现RS编/译码应用
短句来源
     Principle and Application of 8-Digit-LCD Decoder Driver MAX7232BF
     8位液晶译码驱动MAX7232BF的原理及应用
短句来源
     Realization of FPGA Based 5B6B Encoder/Decoder in Fiber Digital Communication System
     光纤数字通信系统5B6B编译码的FPGA实现
短句来源
     A variable RS decoder with IP core circuit is designed in this paper,and the circuit can decode RS(15,5),RS(15,7),RS(15,9) and RS(15,11).
     设计出一种码长可以变化的RS码译码器IP核电路,可进行RS(15,5)、RS(15,7)、RS(15,9)以及RS(15,11)的译码
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      decoder
    Information is used by the decoder algorithms to design the permissible packings and their esquisses.
          
    Decoder design relied on the block representations of packing.
          
    The results of numerical experiment and comparative analysis of decoder operation were presented in conclusion.
          
    The decoder constructs an estimate of the transmitted sequence of pairs, and the kth decoding error is introduced as the event that the pair (mk,tk) does not belong to this sequence.
          
    In convolutional coding, code sequences have infinite length; thus, a maximum-likelihood decoder implies an infinite delay.
          
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    In this paper a brief description on the fundamental theory and operational features of the six-hole ferrite core is given. Emphasis is given on an indicating circuit for a binary-decimal decoder made of such cores. A detailed analysis was made on the decoding cir-cuit. Neon bulbs were used for the indicating lamps of the decimal numbers. The results of test have shown that the operation of the decoder is stable and reliable.

    本文简要地介绍了六孔磁芯的基本原理及其工作特性.文中主要讨论了由六孔磁芯组成的二进位变换成十进位译码器的指示电路,并介绍了它的设计方法和实验结果.在设计过程中,我们对译码器电路作了较为详细的分析,并设计出完整的译码器指示电路图.采用氖灯作为十进位数字的指示灯.实验证明,该译码器工作是既稳定又可靠的.

    Mapping criteria for 4-time-4-frequency coded diversity techniques are firstly analysized so as to obtain the conditions for selecting a set of allowable codewords and the set itself. Then, principles for composing a coder-decoder and methods for extracting synchronizing information from signals are presented. And lastly, the probabilities of error are evaluated.

    本文首先对四时四频编码分集技术的配置准则进行了分析,从而得出选择许用码组集合的条件及许用码组集合,其次,提出了编译码器的组成原理和从信号中提取同步信息的方法,最后,计算了误码率。

    An experimental 1024-bit MOS RAM was fabricated by the P-channel silicon gate process. The design is of the standard 4-transistor cell type, but with some modifications in the peripherial circuits: 1. a grounded device, which is controlled by the internal clock, being used in series with the address decoder, to cut off the dc path, reducing the power ; 2. a clocked single transistor being used as a gate to simplify the address latch; and 3. a grounded device of low transconductance added to the word line,...

    An experimental 1024-bit MOS RAM was fabricated by the P-channel silicon gate process. The design is of the standard 4-transistor cell type, but with some modifications in the peripherial circuits: 1. a grounded device, which is controlled by the internal clock, being used in series with the address decoder, to cut off the dc path, reducing the power ; 2. a clocked single transistor being used as a gate to simplify the address latch; and 3. a grounded device of low transconductance added to the word line, raising the noise margin.

    本文介绍一种1024位MOS随机存储器电路。采用P沟硅栅工艺,标准的四管单元结构。电路设计的主要特点是:1.在地址译码器中串入由内部时钟控制的接地管,完全消除了直流通路,使功耗大大降低;2.地址码封锁电路采用了一种由时钟控制的单管门形式,简化了电路;3.字线通过一个小跨导的放电管接地,提高了抗干扰能力。

     
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