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cache     
相关语句
  缓存
     Completion of dynamic cache in JSP2.0
     在JSP2.0中实现动态缓存
短句来源
     Research of Mobile Databases Cache Algorithms Based on Mobile Agent
     基于Mobile Agent的移动数据库缓存算法研究
短句来源
     Cache Replacement Algorithm for Hybrid P2P Media Streaming
     混合P2P流媒体的缓存替换算法研究
短句来源
     Research of data cache technology based on cache-network
     基于Cache网络数据的数据缓存技术研究
短句来源
     Web Cache Mechanism Based on LRU Algorithm
     基于LRU算法的Web系统缓存机制
短句来源
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  高速缓存
     Design of Storage System Cache Based on RAID50
     基于RAID50的存储系统高速缓存设计
短句来源
     Investigation on the improvement of network I/O performance of Web cache servers
     Web高速缓存服务器网络I/O操作性能存在的问题及改善途径
短句来源
     Web Cache and its Applications in Satellite Internet
     Web高速缓存及其在卫星Internet中的应用
短句来源
     In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory(SPM). A720T processor takes ARM7TDMI as processor core, integrating 8KB Cache.
     为了在实际芯片系统中实现嵌入式SRAM设计以及验证本文提出的优化方法,本文以Garfield20系统芯片1为实验平台,该芯片内嵌A720T嵌入式微处理器和片上存储器(Scratch-Pad memory,SPM),其中A720T处理器以ARM7TDMI为内核,集成8K byte高速缓存(Cache)。
短句来源
     Application of Cache and Process of Data Exchange
     浅谈高速缓存(Cache)的应用
短句来源
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  高速缓冲存储器
     IM-bit CMOS Synchronous Fast SRAM Ideal for Secondary cache Memories for Pentium~(TM), PowerPC~(TM) uPD431132L /uPD431232L
     用作Pentium~(TM),Power PC~(TM)的二次超高速缓冲存储器的理想1兆位CMOS同步快速SRAM μPD431132L/μPD431232L
短句来源
     A 1.8-V 64-kb four-way set-associative CMOS cache memory implemented by 0.18μm/1.8V 1P6M logic CMOS technology for a super performance 32-b RISC microprocessor is presented. For comparison,a conventional parallel access cache with the same storage and organization is also designed and simulated using the same technology.
     采用 0 .1 8μm/ 1 .8V1 P6 M数字 CMOS工艺设计并实现了一种用于高性能 32位 RISC微处理器的 6 4 kb四路组相联片上高速缓冲存储器 (cache) .
短句来源
     In the background of Oracle data base and PL/SQL language, this essay explains the efficiency methods to improve the ETL program processing efficiency in three aspects: Index and SQL sentence optimization、Shared Pool adjustment and Database Buffer Cache adjustment.
     本文以Oracle数据库和PL/SQL语言为背景从优化索引和SQL语句、调整共享池、调整缓冲区高速缓冲存储器三方面详细阐述了提高ETL程序执行效率的方法。
短句来源
     The Cache and The Virtual Memory in 32-bit Microprocessor
     32位微处理器的高速缓冲存储器和虚拟存储器
短句来源
     The Application of High Speed Cache in 386 Computer Serial
     386以上档次微机高速缓冲存储器的应用
短句来源
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  “cache”译为未确定词的双语例句
     The Design and Simulation of High Efficient Cache Protocol in Multi-processors System
     多处理器系统中高效Cache协议的实现方案设计与模拟
短句来源
     The Research on Shared Multi-ported Data Cache Architecture of SCMP
     SCMP中共享多端口数据Cache结构的研究
短句来源
     Research on High Performance Cache and Memory System
     高性能存储系统研究
短句来源
     A CACHE IN RECURSIVE FUNCTIONS
     递归函数中的 Cache
短句来源
     REAL ADDRESS CACHE AND VIRTUAL ADDRESS CACHE
     实地址CACHE与虚地址CACHE
短句来源
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  cache
We carried out a quantitative structure-activity relationship (QSAR) study of caffeoyl naphthalene sulfonamide derivatives via the software WIN CAChe 6.1 and STATISTICA to improve its activity.
      
In pursuit of better anti-HIV drugs, quantitative structure-activity relationship (QSAR) studies were performed on a series of aryl sulfonamide HIV protease inhibitors using Win CAChe 6.1.
      
PM3 calculations performed by MOPAC 2000 associated with Cache pro.
      
On the basis of a cache interference model, formulas are obtained that make it possible to accurately compute tiling parameters.
      
In this paper, we describe experiments on automatic verification of a number of cache coherence protocols with the SCP4 supercompiler (an optimizer of programs written in the REFAL-5 functional language).
      
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HDS-9 is a data processing system with high speed and large capacity main memory. Some techniques, such as multiprocessor organization, pipeline, virtual memory, ring-protection of main memory, multiple memory modules with address interleaving, cache, RAS and 1/O standard interface, have been employed in the system. A simple form of single-arm-latch has been adopted. Operating system used in HDS-9 is symmetric to each processor. The techniques mentioned above and their implementation are described in this...

HDS-9 is a data processing system with high speed and large capacity main memory. Some techniques, such as multiprocessor organization, pipeline, virtual memory, ring-protection of main memory, multiple memory modules with address interleaving, cache, RAS and 1/O standard interface, have been employed in the system. A simple form of single-arm-latch has been adopted. Operating system used in HDS-9 is symmetric to each processor. The techniques mentioned above and their implementation are described in this paper.

HDS-9是一台速度高(双处理机500万次/秒)、容量大(主存512K字),主要用于数据处理的计算机系统。此机在系统结构上采用多重处理机结构,流水线控制技术,虚拟存储器技术,存储器环状保护技术,存储器多模交叉访问,高速缓冲技术,RAS技术,统一标准接口的I/O系统;在工艺技术方面采用高密度组装技术,用SSI-TTL电路组成单臂门闩触发器系统;在系统软件方面采用匀称或平等的操作系统来处理多重处理机关系。 本文着重讨论了多重处理机结构,虚拟存储器,Cachc缓冲技术以及流水线控制技术有关方面问题和实施途径。

A discussion is made on the consistency of information between Cache and Main Memory (MM) in uniprocessor, processor and I/O, and multiprocessor systems. The causes of non-consistency are described and analysed. Several approaches leading to their solution are given, and some points are mentioned for implementation.

本文讨论了单处理机内部、处理机与I/O系统、多重处理机系统中的Cache-MM信息一致性问题。着重讨论了引起Cache-MM信息不一致的原因,并对这些原因进行分析,提出一些具体可行的解决方案,指出了在实施这些方案时应该注意的一些问题。

This paper describes a scheme of virtual memory with high speed, large capacity cache. This virtual memory uses hardware address mapping mechanism to translate address from virtual to real, as the high speed cache exists, the speed matching problem between CPU and memory can be better to be soleved, besides, it saves memery space and decreases time overhead for address translation since there is no need to store the address mapping table in main memory.

本文阐述一个具有大容量的高速缓存虚拟存贮系统方案设计,其特点是使用硬件地址翻译机构实现从逻辑地址到实地址的转换,并带有一个32K容量的Cache,以达到既加快地址翻译速度,又节省内存空间,并较好地解决CPU与内存的速度匹配的目的.

 
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