Secondly, the characteristics of DM642, such as the instruction set, the data channels, the memory system, and the pipelining framework, are introduced, and the impacts of these characteristics are analyzed.
It introduces the principle of 3DES encryption algorithm and descripes the achievement of design on FPGA In the design,pipelining technology is used to improve its running speed,in order to enhance the flexibility,input and output interfaces are involved Besides,all the modules are programmed in hardware description language(VHDL) At last,download to FPGAStratix
介绍了 3 DES加密算法的原理并详尽描述了该算法的 F PGA设计实现 ,设计中还采用了流水线技术来提高速度 ,添加了输入和输出接口的设计以增强应用的灵活性 ,各模块均用硬件描述语言 V HDL 实现 ,最终下载到 F PGA芯片Stratix中。
This thesis investigated the implementation of the modified Euclidean (ME) algorithm which was extensively used in RS decoder and proposed a low complexity structure of ME algorithm by using pipelining technique and multiplexing finite field multiplier.
In this paper,the output signal time schedule of CCD processing module in star sensor is analyzed in detail,then the parallel processing and pipelining is presented for improving the efficiency of star image processing. The parallel processing and pipelining between CCD and DSP are realized by using HOLD of DSP and CPLD.
Combining the principles of pipelining and parallelism of DSP with IDCT theory, we concentrate on the use of Multiply-Accumulate Unit of MCF5272 by merging the operations of addition and multiplication, and realize two dimension of IDCT with one dimension of IDCT efficiently.