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parity checks
相关语句
  奇偶校验
     Demodulating BPSK signal by calculating number of pulses during every code and making parity checks
     用脉冲计数和奇偶校验法解调BPSK信号
短句来源
  “parity checks”译为未确定词的双语例句
     A FREQUENCY DOMAIN APPROACH TO OBTAIN ALL PARITY CHECKS
     得到误差检验式的频域方法
短句来源
     Then it is proved that all parity checks can be generated from the basis of the left null space of the polynomial matrix [C'(zI-A)'].
     由此出发,证明了只要得到多项式矩阵[C'(zI-A)']'的左零空间的基,则可得到所有的误差检验式;
短句来源
  相似匹配句对
     FACTORS AND PARITY
     因子与奇偶性
短句来源
     A FREQUENCY DOMAIN APPROACH TO OBTAIN ALL PARITY CHECKS
     得到误差检验式的频域方法
短句来源
     Demodulating BPSK signal by calculating number of pulses during every code and making parity checks
     用脉冲计数和奇偶校验法解调BPSK信号
短句来源
     Analyzing the Parity of Function
     论函数的奇偶性
短句来源
     Checks and calculations for location of holes
     位置度的检验计算
短句来源
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  parity checks
Then distinguishing attacks can be achieved through these biased parity checks.
      
On the basis of these linear approximations and the periods of the registers, parity checks with noticeable biases are found.
      
Dual codes are finally introduced as families of parity checks on a given modular code, and related to the standard theory of 2D behaviors.
      
In this paper a related algorithm is presented that obtains the linear complexity of the sequence requiring, on average for sequences of period 2n,n≥0, no more than 2 parity checks sums.
      
We here recover the usual assumption on the number of parity checks, which should be greater than or equal to the number of faults.
      
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This paper systematically describes software table algorithm for implementing polynomial error detection codes with a microprocessor.In order to speed up the implementation of polynomial error detection codes, J .S.Whiting proposed software method, but it is only suited to the case in which the number of information bits are the integral multiples of the number of the parity-check bits[1].The algorithm presented in this paper is established on the basis of J,S. Whiting's results.It applies not only...

This paper systematically describes software table algorithm for implementing polynomial error detection codes with a microprocessor.In order to speed up the implementation of polynomial error detection codes, J .S.Whiting proposed software method, but it is only suited to the case in which the number of information bits are the integral multiples of the number of the parity-check bits[1].The algorithm presented in this paper is established on the basis of J,S. Whiting's results.It applies not only to the integral multiples but also to non -integral multiples. Mathematical derivation is given in this paper, Thus the algorithm has wide-ranging adaptability .The larger the rate R of a code, the better the effect .Finally, several examples of its application are given.

本文系统地描述了在微型机上实现多项式检错码的软件表算法,把J.S.whiting提出的信息位长度是校验位的整数倍的软件表算法推广到非整数倍的更为一般的情形,给出了算法的数学推证,因此本文提出的方法具有普遍适用性。最后举例说明了这些算法的应用。

Tzeng and Zimmermann showed that the Goppa codes with L=GF(qm), g(z)=[(z-β1) (z -β2)]a (a≥1) become cyclic after being extended by an overall parity check. Recently, Tzeng and Yu showed if a = l the Goppa codes with L=GF (qm) can be extended to cyclic codes, then g(z) is quadratic. In this paper, a further necessary condition is presented. Therefore the sufficient and necessary conditions for extending Goppa codes with L = GF(qm) to cyclic codes are found.

Tzeng和Zimmermann指出,令L=CF(q~m),g(z)=[(z-β_1)(z-β_2)]~a(a≥1)的Goppa码增加一个总计校验位后可扩展成循环码。最近Tzeng和Yu又指出,当a=1时,L=GF(q~m)的Goppa码可扩展成循环码,其必要条件是g(z)为二次的。本文推广了这一必要条件,指出a为小于q~m的正整数,g(z)=[(z-β_1)(z-β_ 2)]~a。是L=GF(q~m)的Goppa码可扩展成循环码的必要条件。

The DG-1 parity check technique is described in this paper. The dynamic configuration of CPU and the structural principles of MOS memory for Hamming codes are introduced and the fault probability in CPU and MOS memory is analyzed. On this bases, the reliability of DG-1 is evaluated.

本文对DG-1型计算机的奇偶检测技术及CPU动态配置下的可靠性、可维性以及具有Hamming编码MOS存贮器的可靠性、可维性作了详细介绍和分析。文末还对DG-1的可靠性、可维性进行了简要综述。

 
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