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a lcd driver circuit
相关语句
  液晶驱动电路
     The circuit structure and its VLSI design and implementation of a low power embedded microcontroller is presented. Taking advantage of EDA, we design the chip which has the multi-clock system, Ha Vard structure and two pipeline stages, and achieve a LCD driver circuit within the chip. Its instruction set adopt is reduced to like that of universal 8 - bit PIC16C5X.
     介绍了一个低功耗嵌入式微控制器的电路结构及其VLSI的实现,该芯片利用EDA辅助设计实现了多时钟系统、哈佛结构、两级流水线结构以及内置液晶驱动电路,其指令集采用了类似通用八位机PIC16C5X的精简指令集。
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  “a lcd driver circuit”译为未确定词的双语例句
     Additionally,a LCD driver circuit is implemented by the SOPC.
     同时,系统还实现了液晶显示屏(LCD)的硬件驱动。
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  相似匹配句对
     A Circuit of LCD Driver with I 2C-Bus
     一种带I~2C总线的LCD驱动电路
短句来源
     A Clock Generation Circuit in LCD Driver and Controller
     LCD驱动控制时钟电路的设计
短句来源
     Design of LCD driver circuit
     一种液晶显示器驱动电路的设计
短句来源
     Additionally,a LCD driver circuit is implemented by the SOPC.
     同时,系统还实现了液晶显示屏(LCD)的硬件驱动。
短句来源
     Design of A MPU Interface Circuit in STN LCD Driver
     基于STNLCD驱动控制芯片的MPU接口电路的设计
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A LCD driver circuit is presented in the paper. The logic voltage signal is level-shifted to the LC drive voltage, and select one of the four levels (V0,V2,V3,V5) based on theFR and !DISPOFF signals to the pin.

介绍了一种液晶显示驱动电路。该电路将逻辑电压信号转变成LC驱动电压,并选择基于FR信号和!DISPOFF信号的四级电位(V0,V2,V3,V5)的其中之一到输出管脚。

The circuit structure and its VLSI design and implementation of a low power embedded microcontroller is presented. Taking advantage of EDA, we design the chip which has the multi-clock system, Ha Vard structure and two pipeline stages, and achieve a LCD driver circuit within the chip. Its instruction set adopt is reduced to like that of universal 8 - bit PIC16C5X. Fabricating the microcontroller in 0.5 μm CMOS technology, its power dissipation decreased enormously through some effective methods.

介绍了一个低功耗嵌入式微控制器的电路结构及其VLSI的实现,该芯片利用EDA辅助设计实现了多时钟系统、哈佛结构、两级流水线结构以及内置液晶驱动电路,其指令集采用了类似通用八位机PIC16C5X的精简指令集。通过采用各种有效的措施,在0.5μm的CMOS工艺条件下,其功耗大大降低。

As digital storage oscilloscope(DSO) sampling rate raising rapidly,the traditional single-processor data processing system(DPS) is difficult to meet the present needs.A DPS based on the system on programmable chip(SOPC) is designed for DSO with 1 GHz sampling rate.In this DPS, an interface and two buffers are planned for the analog-to-digital converter; a special micro controller unit based on Altera Nios II/f soft core is designed;four parallel processing circuits are created to meet complex arithmetical...

As digital storage oscilloscope(DSO) sampling rate raising rapidly,the traditional single-processor data processing system(DPS) is difficult to meet the present needs.A DPS based on the system on programmable chip(SOPC) is designed for DSO with 1 GHz sampling rate.In this DPS, an interface and two buffers are planned for the analog-to-digital converter; a special micro controller unit based on Altera Nios II/f soft core is designed;four parallel processing circuits are created to meet complex arithmetical operations of DSO.Additionally,a LCD driver circuit is implemented by the SOPC.The DPS has high performance,low power consumption,and considerable integration.

基于传统单处理器系统有限的数据处理能力正逐渐成为示波器整机的瓶颈,作者设计了一种基于可编程系统芯片(System on programm ablech ip,SOPC)结构,用于1 GHz采样速率数字存储示波器(Digital storageos-cilloscope,DSO)的数据处理系统。系统中,根据模数转换器特征为其设计了具有数据缓存功能的接口单元;以A ltera Nios II/f软核为基础完成了专用微处理器的设计;针对DSO数据处理特征构建了4个并行处理电路;同时,系统还实现了液晶显示屏(LCD)的硬件驱动。SOPC结构的引入,使得该系统在具备强大数据处理能力的同时,具有低功耗和高集成度的特点。

 
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