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self testing     
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  自测试
     This paper introduces some basic concepts and modeling methods in low power testing, analyzes the causes of increased power consumption, discusses some current practices of power optimization, and finally presents an at speed low power self testing method for the high performance microprocessor.
     首先介绍低功耗测试技术中的基本概念和功耗建模方法 ,分析测试过程中功耗升高的原因 ,对已有的几种主要的降低测试功耗方法进行详细分析 ,最后给出一种高性能微处理器的真速低功耗自测试方法
短句来源
  自我测试
     The paper discusses the process from design to accomplishment in general system and subsystem, focuses on the design of frame architecture, the constitutions of function, at the same time the article lays special stress on design in details and implement of functions at the core of the assignment subsystem and self testing subsystem.
     文中主要叙述了教师口语网络学习系统的总体设计以及部分子系统的开发实现过程,重点阐述了辅助学习系统的框架结构的设计、总体功能模块的构成以及作业子系统、自我测试子系统的详细设计与核心功能的实现。
短句来源
     Stunts actually is a kind of self testing exercise. It is developed from some folk games in south America.
     stunts实为一种力的自我测试运动,它来自于南美的民间游戏。
短句来源
  自校验
     The system has the capability of self testing, data sampling, data processing and communication.
     系统具有自校验,数据采集、处理,数据通信等功能。
短句来源
  “self testing”译为未确定词的双语例句
     Built-In Self Testing Logic for Static RAM
     静态 RAM 的内建自测逻辑
短句来源
     New Method of Built In Self Testing for Pulse Doppler Radar Digital Signal Processor
     脉冲多普勒雷达数字信号处理机机内测试的新方法
短句来源
     The Design and Realization of On-line Testing and Self testing System and Testing Database on the Basis of Campus Intranet
     网上考试自测系统及题库的设计与实现
短句来源
     In this paper, we discuss some methods for resist disturbance design in computer based instrument,including isolation,WDT,timer cycle,self testing,self regulation etc.
     本文以一个多功能测试仪为目标仪器,对计算机化仪器的抗干扰设计方法进行了实验探讨,包括干扰隔离、系统自检、定时循环、故障监测与恢复、放大器自校、选用抗干扰性强的器件等,实验收到了比较好的效果
短句来源
     Its operation principles and key techniques in software and hardware design,self testing method and anti interference measures are described.
     主要分析了该变送器的工作原理、硬件电路、软件设计、自检方法以及抗干扰措施等关键技术。
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      self testing
    The merging method attempts to obtain the self testing systolic array at minimal cost in terms of area and speed.
          
    We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits.
          
    We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing.
          
    We presented a low-cost implementation of a self-testing adder which indicates a stuck-at-fault by oscillations at the carry-out output.
          
    We call it application-level self-testing to distinguish it from our NCP-level self-testing.
          
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    A reconfigurable redundancy management strategy for a triplex DFBW flight control system is discussed in this paper. The strategy consists of redundancy and control law reconfiguration after 1 st, 2 nd and 3rd failures. Every part of the system uses both the comparison monitored and the self-tested schemes. With the combination of two monitors schemes the functional range of reconfigurable strategy can be expanded, and high system reliability can be achieved. The computer verification results for...

    A reconfigurable redundancy management strategy for a triplex DFBW flight control system is discussed in this paper. The strategy consists of redundancy and control law reconfiguration after 1 st, 2 nd and 3rd failures. Every part of the system uses both the comparison monitored and the self-tested schemes. With the combination of two monitors schemes the functional range of reconfigurable strategy can be expanded, and high system reliability can be achieved. The computer verification results for reconfigurable strategy are presented. The reconfigurable management software has been designed, and the architectures for all of software moduls and its interfaces are introduced. It has been shown that the key factor impact on feasibility of the strategy is the data transmitted rate, especially the across-channel data transmitted rate.

    本文论述了三余度数字式电传飞行控制系统的余度重构管理策略,包括对重构管理提出的合宜指标、各次故障的余度重构和控制律重构的设计原理及其验证结果。此外,概述了重构管理软件的设计和实时可行性问题。

    A method of fault location using MPDS (Minimum path Difference Set) for self-testing microcomputer system is presented in this paper.Based on the sufficient analysis of microcomputer hardware, the flows of data or control can be helpful for fault modeling. Test generation is described by MPDS. The aim is that fault is located at IC' chip as accurate as possible.

    本文提出最小路径差集定位法,对微机系统的自测试问题进行了探索。在对微机系统硬件结构充分分析的基础上,根据所建立的故障模型,分别用数据流或控制流的最小路径差集产生测试方法,尽量使故障定位到片(IC'chip)。

    A binary-working/ternary-testing (B/T for short) self-testing system is a special ternary logic system. Normally, it operates in binary mode, thus it is compatible with ordinary binary systems. The third logic value (the middle value) can be used as a fault indicating signal, or in off-line testing. B/T self-checking combinational systems have been studied in [1]. This paper extends the study to sequential systems. First, the structures of B/T R-S flip-flops, B/T D flip-flops and...

    A binary-working/ternary-testing (B/T for short) self-testing system is a special ternary logic system. Normally, it operates in binary mode, thus it is compatible with ordinary binary systems. The third logic value (the middle value) can be used as a fault indicating signal, or in off-line testing. B/T self-checking combinational systems have been studied in [1]. This paper extends the study to sequential systems. First, the structures of B/T R-S flip-flops, B/T D flip-flops and B/T J-K flip-flops are given. Then their fault characteristics are analysed. Finally, a general conclusion on B/T self-checking sequential systems is drawn.

    二值工作三值检测(简称为B/T)自校验系统是一种特殊的三值逻辑系统。正常时,系统工作于二值状态,因此可与一般的二值系统兼容。其第三个逻辑值(中间逻辑值)用作故障指示信号,或在脱机测试时应用。文[1]研究了B/T自校验组合系统。本文将该研究扩展至时序系统,先逐步给出了B/T R-S、D、J-K等触发器的构成方案,分析了它们的故障特性。在此基础上得出了B/T自校验同步时序系统的一般结论。

     
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