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area penalty
相关语句
  区域惩罚划分的
     Parallel multi-objective genetic algorithm by adding area penalty
     按区域惩罚划分的并行多目标遗传算法
短句来源
  “area penalty”译为未确定词的双语例句
     Results show that the proposed scheme can reduce 22.9% of test time in average (up to 52% for one circuit) while area penalty is an increase of 1.4% in average.
     结果表明,本文提出的方案与等长序列重复播种的内建自测试方案比较, 平均至少能减少近22.9%的测试时间(最多达52%),而电路面积平均只增加1.4%。
     The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.
     与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积.
短句来源
     The experiments on ISCAS85 and ISCAS89 benchmark circuits demonstrate that the scheme can reduce 36.22% of test application time in average(up to 57.49% at most),while area penalty increases only 4.41% in average.
     ISCAS85和ISCAS89电路的实验表明,同定长序列重复播种测试码生成相比较,平均减少近36.22%的测试时间(最多57.49%),面积增加仅为4.41%.
短句来源
     As the lengths of the test sequences are variable, the proposed scheme can reduce test application time significantly while keeping low area penalty and high fault coverage.
     但由于重播种子产生的伪随机测试向量序列的长度可不同,因而, 测试向量总长度可比等长序列方案短,测试施加时间可减少,而增加的硬件开销甚少,且故障覆盖率和等长序列方案相同。
  相似匹配句对
     In the area, J.
     这方面,J.
短句来源
     The penalty area was the main fumble area.
     罚球区是失球的主要区域。
短句来源
     The penalty area was the main fumble one.
     罚球区是失球的主要区域;
短句来源
     In the study area .
     长期以来,在教师教育问题研究中,研究者们关注的是中小学教师的发展。
短句来源
     Penalty's Functions
     刑罚的功能
短句来源
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  area penalty
Experimental results show a significant reduction of switching activity without area penalty compared with previous publications.
      
Most of published results show that the reduction of switching activity often trades with area penalty.
      
The results represent the average area penalty for the 14 benchmark circuits.
      
The test schedule obtained for a power limit of 900mW and area penalty limit of 3.5 is shown in Table 3.
      
The point at which the winglet induced-drag benefits begin to outweigh their wetted area penalty is seen to depend on the state of the boundary layer.
      
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A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming (MLP) problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%,...

A fine-grain sleep transistor insertion technique based on our simplified leakage current and delay models is proposed to reduce leakage current. The key idea is to model the leakage current reduction problem as a mixed-integer linear programming (MLP) problem in order to simultaneously place and size the sleep transistors optimally. Because of better circuit slack utilization, our experimental results show that the MLP model can save leakage by 79.75%, 93.56%, and 94.99% when the circuit slowdown is 0%, 3%, and 5%, respectively. The MLP model also achieves on average 74.79% less area penalty compared to the conventional fixed slowdown method when the circuit slowdown is 7%.

首先给出一种泄漏电流和延时的简化模型,并且在此基础上提出了一种降低泄漏电流的细粒度休眠晶体管插入法.该方法的核心是利用混合整数线性规划方法同时确定插入细粒度休眠晶体管的位置和尺寸.从实验结果可以发现,由于这种方法更好地利用了电路中的延时余量,所以在电路性能不受影响的情况下可以减小79.75%的泄漏电流;并且在一定范围内放宽电路的延时约束可以更大幅度地降低泄漏电流.与传统的固定放宽延时约束的方法相比较,当延时约束放宽7%时,这种方法可以节约74.79%的面积.

A generation of reseeding test pattern with variable lengths of test sequences is proposed.It uses reseeding technology and the pseudo-random test sequences generated by seeds may have different lengths.Every seed can generate pseudo-random test sequences with variable length.The lengths generated are whole length L,L/2,3L/4,L/4 and 1.This technology with variable length can cut redundant test vectors effectively,and reduces the test application time.The experiments on ISCAS85 and ISCAS89 benchmark circuits...

A generation of reseeding test pattern with variable lengths of test sequences is proposed.It uses reseeding technology and the pseudo-random test sequences generated by seeds may have different lengths.Every seed can generate pseudo-random test sequences with variable length.The lengths generated are whole length L,L/2,3L/4,L/4 and 1.This technology with variable length can cut redundant test vectors effectively,and reduces the test application time.The experiments on ISCAS85 and ISCAS89 benchmark circuits demonstrate that the scheme can reduce 36.22% of test application time in average(up to 57.49% at most),while area penalty increases only 4.41% in average.

提出了一种变长重复播种测试码生成方法.该方法使用重复播种技术,但是每个种子产生的伪随机测试码序列的长度不同.每个种子可以产生长度为全长L,3L/4,L/2,L/4,和单个种子1的伪随机测试码序列.该变长技术的一个优点是可以有效地截去大量冗余伪随机测试码,减少测试施加时间.ISCAS85和ISCAS89电路的实验表明,同定长序列重复播种测试码生成相比较,平均减少近36.22%的测试时间(最多57.49%),面积增加仅为4.41%.

>=A reseeding BIST scheme with variable lengths of test sequences is proposed in this paper. It uses reseeding technology and the pseudo-random test sequences generated by seeds may have different lengths. The same as the reseeding scheme with constant length of test sequences proposed in [1,2], the proposed scheme also uses the tests for testing hardly detected faults by primary pseudo random sequence as seeds and the seeds are stored in ROM with compression technology. As the lengths of the test sequences...

>=A reseeding BIST scheme with variable lengths of test sequences is proposed in this paper. It uses reseeding technology and the pseudo-random test sequences generated by seeds may have different lengths. The same as the reseeding scheme with constant length of test sequences proposed in [1,2], the proposed scheme also uses the tests for testing hardly detected faults by primary pseudo random sequence as seeds and the seeds are stored in ROM with compression technology. As the lengths of the test sequences are variable, the proposed scheme can reduce test application time significantly while keeping low area penalty and high fault coverage. The proposed scheme realized with realistic method is given and is applied to ISCAS85 benchmark circuits. Results show that the proposed scheme can reduce 22.9% of test time in average (up to 52% for one circuit) while area penalty is an increase of 1.4% in average.

本文提出一种变长序列重复播种的内建自测试方案,该方案使用重复播种技术,每个种子所产生的伪随机测试向量的序列长度不同。和文献[1,2]的等长序列重复播种的内建自测试方案一样,本文提出的方案也采用检测原始伪随机向量序列难以检测的故障的测试作为种子,并使用压缩技术把种子保存在ROM中。但由于重播种子产生的伪随机测试向量序列的长度可不同,因而, 测试向量总长度可比等长序列方案短,测试施加时间可减少,而增加的硬件开销甚少,且故障覆盖率和等长序列方案相同。本文给出了实现变长序列重复播种内建自测试方案的具体方法,并把它应用于ISCAS85基准电路。结果表明,本文提出的方案与等长序列重复播种的内建自测试方案比较, 平均至少能减少近22.9%的测试时间(最多达52%),而电路面积平均只增加1.4%。

 
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