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bit shift register
相关语句
  位移位寄存器
     By fully applying the storage potential of 16 bit shift register LUT(SRL16E),a recursive delay line(RDL) is proposed with the characters of multiplicative decrease of taps number and increase of taps' sample rate.
     利用16位移位寄存器(SRL16E)的存储潜力,设计递归延迟线(RDL);
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  “bit shift register”译为未确定词的双语例句
     For a 5bit shift register, a power savings for above 93% is achieved by PAL 2NF circuit, comparetd with PAL 2N circuit at 10MHz, and can reach 40% at 400MHz. Power dissipation of PAL 2NF circuits is obviously lower than that of PAL 2N homologous circuits.
     五级级联的 PAL - 2 NF反相器 /缓冲器电路在功率时钟频率 1 0 MHz时都比相应的 PAL - 2 N电路节省 93%以上的功耗 ,在 4 0 0 MHz时功耗节省也可达4 0 % .
短句来源
     For a 5bit shift register,power savings above 80% are achieved by two types of EPAL circuits,compared with PAL-2N circuit at 10MHz,and can reach 23% and 50% respectively at 400MHz. The power dissipations of EPAL circuits are obviously lower than that of PAL-2N homologous circuits.
     两种 EPAL的五级反相器 /缓冲器电路在功率时钟频率为 10 MHz时都比相应的 PAL - 2 N电路节省 80 %以上的功耗 ,在 4 0 0 MHz时功耗节省也分别可达 2 3%和 5 0 % .
短句来源
  相似匹配句对
     A Very High Speed 8-Bit Shift Register
     一种超高速八位移位寄存器
短句来源
     register;
     立案阶段;
短句来源
     A Monolithic High Speed 4 Bit Counter/Shift Register IC
     一种单片高速四位计数器/移位寄存器
短句来源
     The Device for Demonstrating the Direction of Direct Current by Using Four-Bit Bidirectional Shift Register
     用四位双向移位寄存器研制的直流电流方向模拟演示仪
短句来源
     The Study of Shift Register in Serial Password
     序列密码中移位寄存器的研究与分析
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  bit shift register
A ten thousand bit shift register has been successfully operated in a film grown on an etch-polished substrate.
      
The transmit scrambler is a 7-bit shift register, with 7 configurable taps.
      
The time staggered code samples are easily gznzrated by driving a two or three bit shift register with your locally generated PN code.
      
The next component in Figure 20 is the timestamp management unit which includes a two-bit shift register file and a priority selection logic.
      
The hardware version is illustrated in Figure 1 by an 8 bit shift register.
      
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A simple and practical technique of cell construction for ASICs is introduced in the paper, with ang-bit shift register as an example. There exist many design techniques for ASICs, which are based on advanced design tools and extensive bases for IC CAD. Without these design environments, ASICs can also be designed in a relatively short time using cell construction design technique. Compared with conventional techniques , it is an excellent method for ASIC design with such features as quick turnaround design...

A simple and practical technique of cell construction for ASICs is introduced in the paper, with ang-bit shift register as an example. There exist many design techniques for ASICs, which are based on advanced design tools and extensive bases for IC CAD. Without these design environments, ASICs can also be designed in a relatively short time using cell construction design technique. Compared with conventional techniques , it is an excellent method for ASIC design with such features as quick turnaround design time, good circuit performance, low design cost and symmetrical layout.

本文以高速八位移位寄存器的研制为例,介绍了一种简便可行的专用集成电路单元结构设计方法。专用集成电路的设计目前有很多方法,但都基于有先进的设计工具和较为丰富的集成电路CAD库。没有这些设计环境,使用单元结构设计方法同样可以较快地设计专用集成电路。与通常的设计相比,这种方法具有设计周期短,电路性能高,设计成本低,版图布局对称等特点,是一种较好的专用集成电路设计方法。

The design of a very high-speed 8-bit shift register and its fabrication process are described in the paper. The cell structure is used for the design of logic,circuit and layout as well as overall planning. A 3-um ECL process is adopted to fabricate the device. A maximum operating frequency of 400MHz has been obtained, which is 40 times higher than that for a conventional TTL or CMOS shift register. The temperature range for the device is -55~85C.

介绍了一种超高速八位移位寄存器的设计和工艺制造技术。采用单元结构设计方法进行逻辑设计、电路设计、版图设计和整体设计,用3μm双埋层对通pn结隔离ECL技术进行工艺制作,其最高工作频率达到400MHz以上,工作温度范围为-55℃~85℃,比常规的TTL或者COMS移位寄存器工作频率高40倍。

A new approach to the design of programmable logic array (PLA) is proposed.This PLAA canbe easily tested and yet, only one extra hardware is added, mainly a m-bit shift register. Themethods of testing the PLA are also detailed. These methods require few test vectors for testing,evaluate the test easily and obtain high fault coverage.

本文提出了一种易测试PLA的新设计,这种设计使PLA易于测试,所增加的硬件只是一个m位移位寄存器.本文还详述了对这种PLA进行测试的方法,该测试方法只需要很少的测试向量,测试结果计算简单,具有很高的故障复盖率.

 
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